Static timing and/or noise analysis are performed on a netlist of an integrated circuit, to
estimate behavior of the netlist and to identify at least one violation by said behavior of a …

Interconnect spacing is getting increasingly smaller in advanced technology nodes, which
adversely increases the capacitive coupling of adjacent interconnect wires. It makes …

Design guidelines for shielding in the presence of power/ground (P/G) noise are presented
in this paper. The effect of P/G noise on crosstalk is analyzed for different line lengths, line …

NBTI is becoming one of the dominant circuit reliability concerns in nano-scale technologies.
We believe that designers can combat NBTI degradation using appropriate circuit …

As VLSI technologies scale down, interconnect performance is greatly affected by crosstalk
noise due to the decreasing wire separation and increased wire aspect ratio, and crosstalk …

Vittal, A. et al.,“Crosstalk Reduction for VLSI, IEEE Transactions on computer-aided design
of integrated circuits and systems, Mar. 1997, vol. 16, No. 3, pp. 290-298. Saxena, P. et al.,“A …

The increasing capabilities of mobile devices and their mobile positioning technologies
have shown great promise in location-enabled applications such as navigation systems …

The continuous scaling trends of interconnect wires in deep submicron (DSM) circuits result
in increased interconnect delay and crosstalk noise. In this work, we develop a new …

Continuous progress in the design and manufacturing of integrated circuits (ICs) has
enabled the integration of more than two billion transistors on the same die with clock …

In this paper, we proposed a side-contact reduced graphene nano-ribbon (SC-RGNR)
interconnect model to reduce crosstalk noise and delay for next generation high …