Spintronic devices: a promising alternative to CMOS devices

P Barla, VK Joshi, S Bhat - Journal of Computational Electronics, 2021 - Springer
The field of spintronics has attracted tremendous attention recently owing to its ability to offer
a solution for the present-day problem of increased power dissipation in electronic circuits …

Architecture of computing system based on chiplet

G Shan, Y Zheng, C Xing, D Chen, G Li, Y Yang - Micromachines, 2022 - mdpi.com
Computing systems are widely used in medical diagnosis, climate prediction, autonomous
vehicles, etc. As the key part of electronics, the performance of computing systems is crucial …

MLiM: High-performance magnetic logic in-memory scheme with unipolar switching SOT-MRAM

B Wu, H Zhu, K Chen, C Yan… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Conventional computing architectures based on the von Neumann structure are suffering
from the severe 'memory wall'issue due to the isolation and speed mismatch between …

Local bit line 8T SRAM based in-memory computing architecture for energy-efficient linear error correction codec implementation

AK Rajput, M Pattanaik - Microelectronics Journal, 2023 - Elsevier
Memory reliability is a critical issue in SRAM-based In-Memory Computing (IMC)
architecture. The rapid advance in transistor technology makes SRAM more sensitive to soft …

Logic‐In‐Memory Characteristics of Reconfigurable Feedback Field‐Effect Transistors with Double‐Gated Structure

Y Shin, J Son, J Jeon, K Cho… - Advanced Electronic …, 2023 - Wiley Online Library
The reconfigurable feedback field‐effect transistors (R‐FBFETs) with a double‐gated
structure are designed and the logic and memory operations of a logic‐in‐memory (LIM) …

Reconfigurable spintronic logic gate utilizing precessional magnetization switching

T Liu, X Li, H An, S Chen, Y Zhao, S Yang, X Xu… - Scientific Reports, 2024 - nature.com
In traditional von Neumann computing architecture, the efficiency of the system is often
hindered by the data transmission bottleneck between the processor and memory. A …

Double MAC on a Cell: A 22-nm 8T-SRAM Based Analog In-Memory Accelerator for Binary/Ternary Neural Networks Featuring Split Wordline

H Tagata, T Sato, H Awano - IEEE Open Journal of Circuits and …, 2024 - ieeexplore.ieee.org
This paper proposes a novel 8T-SRAM based computing-in-memory (CIM) accelerator for
the Binary/Ternary neural networks. The proposed split dual-port 8T-SRAM cell has two …

STDP implementation using multi-state spin− orbit torque synapse

H Ghanatian, M Ronchini, H Farkhani… - Semiconductor Science …, 2021 - iopscience.iop.org
The abundance of data to be processed calls for new computing paradigms, which could
accommodate, and directly map artificial neural network architectures at the hardware level …

Double magnetic tunnel junction two bit memory and nonvolatile logic for in situ computing

AG Qoutb, EG Friedman - Microelectronics Journal, 2023 - Elsevier
In exascale computing, a huge amount of data is processed in real-time. Conventional
CMOS-based computing paradigms follow the read, compute, and write back mechanism …

Effect of helicity on the discrete instability of weak helimagnets

G Sunny, CM Joy, A Prabhu, L Kavitha - Nonlinear Dynamics, 2025 - Springer
The properties of antisymmetric Dzyaloshinsky-Moriya (DM) interaction and helicity in a
ferromagnetic spin chain system is studied. Propogation dynamics of discrete breathers …