Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines

M Abdallah - US Patent 9,842,005, 2017 - Google Patents
A system for executing instructions using a plurality of register file segments for a processor.
The system includes a global front end scheduler for receiving an incoming instruction …

Method for dependency broadcasting through a source organized source view data structure

M Abdallah - US Patent 10,275,255, 2019 - Google Patents
(57) ABSTRACT A method for dependency broadcasting through a source organized source
view data structure. The method includes receiving an incoming instruction sequence using …

Automatic checkpointing and partial rollback in software transaction memory

S Agarwal, M Gupta, SR Kallikote - US Patent 9,569,254, 2017 - Google Patents
While speculatively executing a given one of a plurality of transactions concurrently
executing on a computer, carry out write operations in a local data block, and automatically …

Supporting atomic accumulation with an addressable accumulator

FY Busaba, MK Gschwind, EM Schwarz - US Patent 9,575,890, 2017 - Google Patents
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Method for dependency broadcasting through a block organized source view data structure

M Abdallah - US Patent 9,934,042, 2018 - Google Patents
A method for dependency broadcasting through a block organized source view data
structure. The method includes receiving an incoming instruction sequence using a global …

Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines

M Abdallah - US Patent 9,766,893, 2017 - Google Patents
A method for executing instructions using a plurality of virtual cores for a processor. The
method includes receiving an incoming instruction sequence using a global front end …

Methods, systems and apparatus for predicting the way of a set associative cache

M Abdallah, R Rao, K Avudaiyappan - US Patent 9,904,625, 2018 - Google Patents
A method for predicting a way of a set associative shadow cache is disclosed. As a part of a
method, a request to fetch a first far taken branch instruction of a first cache line from an …

Method for performing dual dispatch of blocks and half blocks

M Abdallah - US Patent 9,811,342, 2017 - Google Patents
A method for executing dual dispatch of blocks and half blocks. The method includes
receiving an incoming instruction sequence using a global front end; grouping the …

Method and apparatus for efficient scheduling for asymmetrical execution units

US Patent 9,632,825, 2017 - Google Patents
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Method for implementing a reduced size register view data structure in a microprocessor

MA Abdallah - US Patent 9,891,924, 2018 - Google Patents
A method for implementing a reduced size register view data structure in a microprocessor.
The method includes receiving an incoming instruction sequence using a global front end; …