Molecular approach to engineer two-dimensional devices for CMOS and beyond-CMOS applications

Y Zhao, M Gobbi, LE Hueso, P Samorì - Chemical Reviews, 2021 - ACS Publications
Two-dimensional materials (2DMs) have attracted tremendous research interest over the
last two decades. Their unique optical, electronic, thermal, and mechanical properties make …

Heat generation and transport in nanometer-scale transistors

E Pop, S Sinha, KE Goodson - Proceedings of the IEEE, 2006 - ieeexplore.ieee.org
As transistor gate lengths are scaled towards the 10-nm range, thermal device design is
becoming an important part of microprocessor engineering. Decreasing dimensions lead to …

Six-band calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness

MV Fischetti, Z Ren, PM Solomon, M Yang… - Journal of Applied …, 2003 - pubs.aip.org
A six-band k⋅ p model has been used to study the mobility of holes in Si inversion layers for
different crystal orientations, for both compressive or tensile strain applied to the channel …

Modeling of electron mobility in gated silicon nanowires at room temperature: Surface roughness scattering, dielectric screening, and band nonparabolicity

S Jin, MV Fischetti, T Tang - Journal of Applied Physics, 2007 - pubs.aip.org
We present a theoretical study of electron mobility in cylindrical gated silicon nanowires at
300 K based on the Kubo-Greenwood formula and the self-consistent solution of the …

Modeling of surface-roughness scattering in ultrathin-body SOI MOSFETs

S Jin, MV Fischetti, TW Tang - IEEE Transactions on Electron …, 2007 - ieeexplore.ieee.org
A rigorous surface-roughness scattering model for ultrathin-body silicon-on-insulator (SOI)
MOSFETs is derived, which reduces to Ando's model in the limit of bulk MOSFETs. The …

Thermal phenomena in nanoscale transistors

E Pop, KE Goodson - 2006 - asmedigitalcollection.asme.org
As CMOS transistor gate lengths are scaled below 45 nm, thermal device design is
becoming an important part of microprocessor engineering. Decreasing dimensions lead to …

Physically based modeling of low field electron mobility in ultrathin single-and double-gate SOI n-MOSFETs

D Esseni, A Abramo, L Selmi… - IEEE transactions on …, 2003 - ieeexplore.ieee.org
In this paper, we have extensively investigated the silicon thickness dependence of the low
field electron mobility in ultrathin silicon-on-insulator (UT-SOI) MOSFETs operated both in …

Analysis of self-heating effects in ultrathin-body SOI MOSFETs by device simulation

C Fiegna, Y Yang, E Sangiorgi… - IEEE Transactions on …, 2007 - ieeexplore.ieee.org
This paper discusses self-heating (SHE) effects in silicon-on-insulator (SOI) CMOS
technology and applies device simulation to analyze the impact of thermal effects on the …

Continuous MOSFET performance increase with device scaling: The role of strain and channel material innovations

DA Antoniadis, I Aberg, CN Chleirigh… - IBM Journal of …, 2006 - ieeexplore.ieee.org
A simple model that links MOSFET performance, in the form of intrinsic switch delay, to
effective carrier velocity in the channel is developed and fitted to historical data. It is shown …

Understanding quasi-ballistic transport in nano-MOSFETs: part I-scattering in the channel and in the drain

P Palestri, D Esseni, S Eminente… - … on Electron Devices, 2005 - ieeexplore.ieee.org
In this paper, and in Part II, Monte Carlo (MC) simulations including quantum corrections to
the potential and calibrated scattering models are used to study electronic transport in bulk …