[HTML][HTML] A brief review of atomic layer deposition: from fundamentals to applications

RW Johnson, A Hultqvist, SF Bent - Materials today, 2014 - Elsevier
Atomic layer deposition (ALD) is a vapor phase technique capable of producing thin films of
a variety of materials. Based on sequential, self-limiting reactions, ALD offers exceptional …

Germanium p-channel FinFET fabricated by aspect ratio trapping

MJH Van Dal, G Vellianitis, B Duriez… - … on Electron Devices, 2014 - ieeexplore.ieee.org
We report scaled Ge p-channel FinFETs fabricated on a 300-mm Si wafer using the aspect-
ratio-trapping technique. For long-channel devices, a combination of a trap-assisted …

Germanium-tin (GeSn) P-channel fin field-effect transistor fabricated on a novel GeSn-on-insulator substrate

D Lei, KH Lee, YC Huang, W Wang… - … on Electron Devices, 2018 - ieeexplore.ieee.org
Germanium–tin (GeSn) p-channel fin field-effect transistor (p-FinFET) was realized on a
novel GeSn-on-insulator (GeSnOI) substrate. The high-quality GeSnOI substrate was formed …

Scaled p-channel Ge FinFET with optimized gate stack and record performance integrated on 300mm Si wafers

B Duriez, G Vellianitis, MJH Van Dal… - 2013 IEEE …, 2013 - ieeexplore.ieee.org
We demonstrate scaled, replacement gate high-k/metal gate p-channel Ge FinFETs
integrated onto 300mm Si wafers for which the best device shows record peak gm, ext= 2.7 …

Monolithically Cointegrated Tensile Strained Germanium and InxGa1-xAs FinFETs for Tunable CMOS Logic

R Joshi, S Karthikeyan… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
In this article, we have evaluated the merits of monolithically cointegrated alternate channel
complementary metal-oxide-semiconductor (CMOS) device architecture, utilizing tensile …

Predictive simulation and benchmarking of Si and Ge pMOS FinFETs for future CMOS technology

L Shifren, R Aitken, AR Brown… - … on Electron Devices, 2014 - ieeexplore.ieee.org
In this paper, we study and compare Si versus Ge pMOS FinFETs at advanced node
dimensions using ensemble Monte Carlo simulations. It is found that due to large external …

Access resistance reduction in Ge nanowires and substrates based on non-destructive gas-source dopant in-diffusion

R Duffy, M Shayesteh, K Thomas, E Pelucchi… - Journal of Materials …, 2014 - pubs.rsc.org
To maintain semiconductor device scaling, in recent years industry has been forced to move
from planar to non-planar device architectures. This alone has created the need to develop …

Impact of negative capacitance effect on germanium double gate pFET for enhanced immunity to interface trap charges

M Bansal, H Kaur - Superlattices and Microstructures, 2018 - Elsevier
In this work, a comprehensive drain current model has been developed for long channel
Negative Capacitance Germanium Double Gate p-type Field Effect Transistor (NCGe-DG-p …

Prediction of robust two-dimensional topological insulators based on Ge/Si nanotechnology

C Delerue - Physical Review B, 2014 - APS
Atomistic tight-binding calculations show that two-dimensional topological insulators can be
obtained using Ge or Ge/Si nanotechnologies. The strong quantum confinement is used to …

Reduction of Reactive-Ion Etching-Induced Ge Surface Roughness by SF6/CF4 Cyclic Etching for Ge Fin Fabrication

XZ Ma, R Zhang, JB Sun, Y Shi… - Chinese Physics Letters, 2015 - iopscience.iop.org
An SF 6/CF 4 cyclic reactive-ion etching (RIE) method is proposed to suppress the surface
roughness and to optimize the morphology of Ge fin, aiming at the fabrication of superior Ge …