A 65nm thermometer-encoded time/charge-based compute-in-memory neural network accelerator at 0.735 pJ/MAC and 0.41 pJ/Update

M Gong, N Cao, M Chang… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
This brief presents an in-memory compute macro for neural-network based controllers
including inference and in-situ weight updates featuring:(1) in-memory multi-bit matrix and …

A historical perspective on hardware AI inference, charge-based computational circuits and an 8 bit charge-based multiply-add core in 16 nm FinFET CMOS

KA Sanni, AG Andreou - … on Emerging and Selected Topics in …, 2019 - ieeexplore.ieee.org
The second wave of AI is about statistical learning of low dimensional structures from high
dimensional data. Inference is done using multilayer, data transforming networks using fixed …

E-MAC: Enhanced In-SRAM MAC Accuracy via Digital-to-Time Modulation

S Seyedfaraji, S Shakibhamedan… - IEEE Journal on …, 2024 - ieeexplore.ieee.org
In this article, we introduce a novel technique called E-multiplication and accumulation
(MAC)(EMAC), aimed at enhancing energy efficiency, reducing latency, and improving the …

OPTIMA: Design-Space Exploration of Discharge-Based In-SRAM Computing: Quantifying Energy-Accuracy Trade-offs

S Seyedfaraji, S Jager, S Shakibhamedan… - Proceedings of the 61st …, 2024 - dl.acm.org
In-SRAM computing promises energy efficiency, but circuit nonlinearities and PVT variations
pose major challenges in designing robust accelerators. To address this, we introduce …

AID: Accuracy improvement of analog discharge-based in-SRAM multiplication accelerator

S Seyedfaraji, B Mesgari… - 2022 Design, Automation …, 2022 - ieeexplore.ieee.org
This paper presents a novel circuit (AID) to improve the accuracy of an energy-efficient in-
memory multiplier using a standard 6T-SRAM. The state-of-the-art discharge-based in …

Neuromorphic Electronics at BioCAS: A 20-year Legacy of Sparking Technology Revolutions

A Akwaboah… - 2024 IEEE Biomedical …, 2024 - ieeexplore.ieee.org
Motivated by the parsimony and robustness of the biological brain at computing, engineers
have, over the last four decades, been emulating neurophysiology in silicon, ie …

CMOS based Ultra-low Power High-Precision Analog Vector Matrix Multiplication Circuit with±0.1% Error for Vision Application

N Mirchandani, A Shrivastava - 2019 IEEE 62nd International …, 2019 - ieeexplore.ieee.org
This paper presents the design of a low power multiplier cell which multiplies an input
voltage with current. The multiplier achieves high precision with±0.1% error for a wide range …

SMART: Investigating the Impact of Threshold Voltage Suppression in an In-SRAM Multiplication/Accumulation Accelerator for Accuracy Improvement in 65 nm CMOS …

S Seyedfaraji, B Mesgari… - 2022 25th Euromicro …, 2022 - ieeexplore.ieee.org
State-of-the-art In-memory processing has recently emerged as the most promising solution
to overcome design challenges related to data movement inside current computing systems …

A Mixed-Signal Successive Approximation Architecture for Energy-Efficient Fixed-Point Arithmetic in 16nm FinFET

K Sanni, A Andreou - 2019 IEEE International Symposium on …, 2019 - ieeexplore.ieee.org
In this work, a mixed-signal architecture, inspired from the widely-popular successive
approximation analog-to-digital converter, is presented as an energy-efficient alternative to …

Parameter Estimation using Random 1 bit Streams (PEERS)

N Zachariah, I Doxas, J Molin - 2021 55th Annual Conference …, 2021 - ieeexplore.ieee.org
Matched filtering is used in radar signal processing for optimal detection of signals in highly
noisy environments. In this paper, we demonstrate a novel method for matched matched …