Chip multicore processors (CMPs) have emerged as the dominant architecture choice for
modern computing platforms and will most likely continue to be dominant well into the …

The commonly used LRU replacement policy is susceptible to thrashing for memory-
intensive workloads that have a working set greater than the available cache size. For such …

A mechanistic model for out-of-order superscalar processors is developed and then applied
to the study of microarchitecture resource scaling. The model divides execution time into …

Miss rate curves (MRCs) are useful in a number of contexts. In our research, online L2 cache
MRCs enable us to dynamically identify optimal cache sizes when cache-partitioning a …

In order to effectively size L2 cache partitions, a quantifiable metric is needed to properly
predict performance as a function of L2 cache size. For page management, Miss Rate …

Emerging Non-Volatile Memories (NVMs) have promising advantages (eg, lower idle power,
higher density, and non-volatility) over the existing predominant main memory technology …

Multicore processors contain new hardware characteristics that are different from previous
generation single-core systems or traditional SMP (symmetric multiprocessing) …

Hardware performance monitoring counters (PMCs) have proven effective in characterizing
application performance. Because PMCs can only be accessed directly at the OS privilege …

The inherent temporal locality in memory accesses is filtered out by the L1 cache. As a
consequence, an L2 cache with LRU replacement incurs significantly higher misses than the …

This paper introduces a novel analytical model for estimating the cache hit ratio as a function
of time. The cache may not reach the steady-state hit ratio when the number of Web objects …