Electrostatic discharges (ESDs) are everywhere-in our homes and businesses. Even the
manufacturers of the electronics experience ESD failures in their factories. Electronic …

An integrated circuit is provided with electrostatic discharge (ESD) protection circuitry (120)
which uses low voltage transistors (N1, N2) to provide protection to a signal pad that …

The use of a substrate pump to achieve uniform npn protection in a multi-finger NMOS is
reported for advanced CMOS technologies with silicide. The novel feature of this device …

With the evolution of semiconductor technology and global diversification of the
semiconductor business, testing of semiconductor devices to systems for electrostatic …

An integrated circuit is provided With electrostatic discharge (ESD) protection circuitry (120)
A substrate region in the semiconductor substrate is enclosed by a ring of highly doped …

This paper presents a layout extraction and verification methodology which targets reliability-
driven I/O design for CMOS VLSI chip, specifically to guard against electrostatic discharge …

In CMOS technologies, the layout and placement of devices and substrate contacts can
have significant impact on the circuit's ESD (electrostatic discharge) performance due to …

Electrostatic discharge (ESD) has been a major concern for IC chip quality. In this paper, the
IC damage phenomena due to ESD and the protection techniques are reviewed. Also, the …

In this work, a substrate triggered HV tolerant lateral NPN (LNPN) design is presented for a
fully salicided, 0.35/spl mu/m, 90/spl Aring/gate oxide, thin-epi, retrograde n-well, bulk …

Due to interactions through the common silicon substrate, the layout and placement of
devices and substrate contacts can have significant impacts on a circuit's ESD (Electrostatic …