[PDF][PDF] Aspect of balanced ternary arithmetic implemented using CMOS recharged semi-floating gate device

H Gundersen - Oslo: Oslo University, 2008 - researchgate.net
Mostly all electronics used in computers today are based on binary logic. However, does the
binary logic have the capacity to be the leading technology in the future? Thus I raise the …

Quadrature oscillator based on novel low-voltage ultra-low-power quasi-floating-gate DVCC

F KHATEB, N KHATIB, J KOTON… - Scientia …, 2018 - scientiairanica.sharif.edu
In this work, a new realization topology of the low-voltage ultra-low-power quadrature
oscillator is presented. This quadrature oscillator utilizes only two active elements, namely …

A novel low-voltage floating-gate CMOS transconductance amplifier with sinh (tanh) shaped output current

Y Berg, S Aunet, O Naess… - ICECS 2001. 8th IEEE …, 2001 - ieeexplore.ieee.org
Presents an ultra low-voltage (ULV) floating-gate (FG) transconductance amplifier. The
amplifier can operate at supply voltages down to 0.3 V in a standard digital double poly …

[PDF][PDF] On the potential of cmos recharged semi-floating gate devices used in balanced ternary logic

H Gundersen - Proceedings of the 17th International Workshop on …, 2008 - Citeseer
Most of the electronic circuits designed today use binary logic. However, will binary logic be
the leading technology in the future, why not uses balanced ternary logic, implemented …

A 0.3 v floating-gate differential amplifier input stage with tunable gain

Y Berg, S Aunet, O Naess… - ICECS 2001. 8th …, 2001 - ieeexplore.ieee.org
In this paper we present a floating-Gate differential amplifier input stage with tunable gain.
The input stage can be used in a differential ultra low-voltage (ULV) floating gate (FG) …

Floating-gate based trimmable current sources

S Sha - 2002 - ora.ox.ac.uk
One of the most crucial building blocks of an electronic system is the digital-to-analogue
converter (DAC) which forms the interface between the digital and analogue component …

A frequency delta-sigma analog-to-digital converter operating at a power-supply voltage of 0.6 V

ME Høvin, DT Wisland, Y Berg, TS Lande - Analog Integrated Circuits and …, 2003 - Springer
This paper describes a delta-sigma analog-to-digital converter operating at a power supply
voltage of 0.6 V. The converter is implemented in a standard AMS 0.6 μm double poly …

[PDF][PDF] A LOW-VOLTAGE SINC DECIMATOR IMPLEMENTED BY A NEW CIRCUIT TECHNIQUE

M Høvin, D Wisland, Y Berg, TS Lande - researchgate.net
In this paper we present a new circuit technique making standard CMOS digital circuits able
to operate at power supply voltages below 1V. This technique is based on lowering the …

[PDF][PDF] COMPLETE REFERENCE LIST

H Gundersen - Citeseer
COMPLETE REFERENCE LIST Page 1 COMPLETE REFERENCE LIST Bibliography
Henning Gundersen Version 1.15 - May 9, 2008 1 Page 2 REFERENCES II References [1] …

A low-voltage sinc/sup 2/decimator implemented by a new circuit technique using floating-gate MOS transistors

M Hovin, D Wisland, Y Berg… - 2002 IEEE International …, 2002 - ieeexplore.ieee.org
In this paper we present a new circuit technique making standard CMOS digital circuits able
to operate at a power supply voltages below 1 V. This technique is based on lowering the …