The evergrowing memory demand fueled by datacenter workloads is the driving force
behind new memory technology innovations (eg, NVM, CXL). Tiered memory is a promising …

With the advancement of processor packaging technology and the looming end of Moore's
law, multi-chip-module (MCM) GPUs become a promising architecture to continue the …

Address translation is a performance bottleneck in data-intensive workloads due to large
datasets and irregular access patterns that lead to frequent high-latency page table walks …

To expand effective memory capacity, hardware memory compression transparently
compresses and packs memory values more densely together in DRAM. This requires …

Device pass-through has been widely adopted by cloud service providers to achieve near
bare-metal I/O performance in virtual machines (VMs). However, this approach requires …

Conventional virtual memory (VM) frameworks enable a virtual address to flexibly map to
any physical address. This flexibility necessitates large data structures to store virtual-to …

Despite being one of the oldest data structures in computer science, hash tables continue to
be the focus of a great deal of both theoretical and empirical research. A central reason for …

Virtual memory translation has become a key performance bottleneck of memory-intensive
workloads in virtualized cloud environments. On the x86 architecture, a nested translation …

Virtual memory systems rely on the page table, a crucial component that maps virtual
addresses to physical addresses (ie, address translation). While the Radix Page Table …

Large pages have been the de facto mitigation technique to address the translation
overheads of virtual memory, with prior work mostly focusing on the large page sizes …