Routing algorithms for NoCs were extensively studied in the last 12 years, and proposals for
algorithms targeting some cost function, as latency reduction or congestion avoidance …

Networks-on-chip need to survive to manufacturing faults in order to sustain yield. An
effective testing and configuration strategy however implies two opposite requirements. One …

Aggressive scaling of CMOS process technology allows the fabrication of highly integrated
chips such as NoC-based MPSoCs. However, fault probability increases when devices' size …

This paper presents a novel low-cost routing algorithm for regular (mesh) topology networks-
on-chip. While deterministic NoC routing algorithms such as XY routing are still widely used …

Fault tolerant design has a key role in current nanometric technologies, leading to research
on fault mitigation techniques for NoC-based MPSoCs. Most of the state-of-the-art papers …

This paper presents an original approach to define a path between two routers in a NoC with
faulty routers. Current state-of-the art adopts non-scalable solutions, using tables to store …

Aèsiraci-Networks-on-Chip are vulnerable to a variety of manufacturing and design factors
making them susceptible to disparate faults that cause corrupted message transfer or even …

Networks-on-chip (NoCs) are key components in many-core chip designs. Dynamic power-
awareness is a new challenge present in NoCs that must be efficiently handled by the …

Mecanismos de tolerância a falhas em MPSoCs são obrigatórios para enfrentar defeitos
ocorridos durante a fabricação ou falhas durante a vida útil do circuito integrado. Por …