Asynchronous design—Part 2: Systems and methodologies

SM Nowick, M Singh - IEEE Design & Test, 2015 - ieeexplore.ieee.org
This two-part article aims to provide both a short historical and technical overview of
asynchronous design, as well as a snapshot of the state of the art. Part 1 covered …

Synchronous full-scan for asynchronous handshake circuits

F Te Beest, A Peeters, K Van Berkel… - Journal of Electronic …, 2003 - Springer
Handshake circuits form a special class of asynchronous circuits that has enabled the
industrial exploitation of the asynchronous potential such as low power, low electromagnetic …

Adding synchronous and LSSD modes to asynchronous circuits

K van Berkel, A Peeters, F te Beest - Microprocessors and Microsystems, 2003 - Elsevier
A synchronous mode as well as a scan mode of operation are added to a large class of
asynchronous circuits, in compliance with LSSD design rules. This enables the application …

A survey about testing asynchronous circuits

S Zeidler, M Krstić - … Conference on Circuit Theory and Design …, 2015 - ieeexplore.ieee.org
Even though the asynchronous design methodology is considered to be a promising
solution to upcoming challenges of designing complex integrated circuits (ICs), it is not …

A multiplexer based test method for self-timed circuits

F te Beest, A Peeters - 11th IEEE International Symposium on …, 2005 - ieeexplore.ieee.org
A new test method for self-timed circuits is presented that only uses multiplexers to make the
majority of combinational feedback loops testable. Combinational feedback loops are …

Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect

A Efthymiou, J Bainbridge… - IEEE Transactions on …, 2005 - ieeexplore.ieee.org
Asynchronous design offers a solution to the interconnect problems faced by system-on-chip
(SoC) designers, but their adoption has been held back by a lack of methodology and …

Testing delay faults in asynchronous handshake circuits

F Shi, Y Makris - Proceedings of the 2006 IEEE/ACM international …, 2006 - dl.acm.org
As a class of asynchronous circuits, handshake circuits are designed to tolerate variation of
gate delays. However, certain timing constraints, such as the bundled data assumption, are …

Test methodology for dual-rail asynchronous circuits

KY Huang, TY Shen, CM Li - Proceedings of the 54th Annual Design …, 2017 - dl.acm.org
With low power and variation-tolerant features, asynchronous have been widely used in
advanced VLSI designs. Testing asynchronous circuits has become a very important …

Design-for-test for asynchronous circuit elements

KY Huang, TY Shen, CM Li - US Patent 10,429,440, 2019 - Google Patents
Various examples of a circuit and a technique for testing the circuit are disclosed herein. In
an example, the circuit includes a data input coupled to a scan multiplexer and a path select …

Testing micropipelined asynchronous circuits

ML King, KK Saluja - 2004 International Conferce on Test, 2004 - ieeexplore.ieee.org
Despite advances in the design of asynchronous circuits, little progress has been made in
their testing or design for testability. This work proposes a new strategy for testing …