Brain-inspired computing needs a master plan

A Mehonic, AJ Kenyon - Nature, 2022 - nature.com
New computing technologies inspired by the brain promise fundamentally different ways to
process information with extreme energy efficiency and the ability to handle the avalanche of …

A 7-nm compute-in-memory SRAM macro supporting multi-bit input, weight and output and achieving 351 TOPS/W and 372.4 GOPS

ME Sinangil, B Erbagci, R Naous… - IEEE Journal of Solid …, 2020 - ieeexplore.ieee.org
In this work, we present a compute-in-memory (CIM) macro built around a standard two-port
compiler macro using foundry 8T bit-cell in 7-nm FinFET technology. The proposed design …

Nn-baton: Dnn workload orchestration and chiplet granularity exploration for multichip accelerators

Z Tan, H Cai, R Dong, K Ma - 2021 ACM/IEEE 48th Annual …, 2021 - ieeexplore.ieee.org
The revolution of machine learning poses an unprecedented demand for computation
resources, urging more transistors on a single monolithic chip, which is not sustainable in …

InFO_SoW (system-on-wafer) for high performance computing

SR Chun, TH Kuo, HY Tsai, CS Liu… - 2020 IEEE 70th …, 2020 - ieeexplore.ieee.org
A novel wafer-scale system integration solution, InFO_SoW (System-on-Wafer), has been
successfully developed to integrate known-good chips arrays with power and thermal …

CSCNN: Algorithm-hardware co-design for CNN accelerators using centrosymmetric filters

J Li, A Louri, A Karanth… - 2021 IEEE International …, 2021 - ieeexplore.ieee.org
Convolutional neural networks (CNNs) are at the core of many state-of-the-art deep learning
models in computer vision, speech, and text processing. Training and deploying such CNN …

Correct-by-construction design of custom accelerator microarchitectures

J Yang, Z Yang, J Casas, S Ray - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Modern application-specific System-on-Chip designs include a variety of accelerator blocks
that customize microcontrollers with domain-specific instruction sets and optimized …

MVP: An Efficient CNN Accelerator with Matrix, Vector, and Processing-Near-Memory Units

S Lee, J Choi, W Jung, B Kim, J Park, H Kim… - ACM Transactions on …, 2022 - dl.acm.org
Mobile and edge devices become common platforms for inferring convolutional neural
networks (CNNs) due to superior privacy and service quality. To reduce the computational …

RISC-V virtual platform-based convolutional neural network accelerator implemented in SystemC

SH Lim, WSW Suh, JY Kim, SY Cho - Electronics, 2021 - mdpi.com
The optimization for hardware processor and system for performing deep learning
operations such as Convolutional Neural Networks (CNN) in resource limited embedded …

Low-Energy Line Codes for On-Chip Networks

B Dabak, M Glenn, J Liu, A Buck, S Yang… - arXiv preprint arXiv …, 2024 - arxiv.org
Energy is a primary constraint in processor design, and much of that energy is consumed in
on-chip communication. Communication can be intra-core (eg, from a register file to an ALU) …

Behavioral Analytics of Consumer Complaints

MS Hossain - AI-Driven Intelligent Models for Business Excellence, 2023 - igi-global.com
In the current study, the author implemented cohort analysis methodology of machine
learning (ML) to assess the rate of consumers' complaint retention behavior toward firms …