Two equalizer filter topologies and a merged equalizer/CDR circuit are described that
operate at 10 Gb/s in 0.13-mum CMOS technology. Using techniques such as reverse …

In the" Terabus" optical interconnect program, optical data bus technologies are developed
that will support terabit/second chip-to-chip data transfers over organic cards within high …

This article presents a 200-Gb/s pulse amplitude-modulation four-level (PAM-4) and 100-
Gb/s non-return-to-zero (NRZ) transmitter (TX) in 28-nm CMOS technology. To achieve the …

The continuous growth of traffic volumes steadily raises the throughput requirements on the
network infrastructure. Additionally, a transformation of the classical TDM-based backbone …

This paper presents the design of an analog-front-end (AFE) integrated into a DSP-based
transceiver for both serial 10 Gbps KR-backplane and long-reach-multimode-fiber (LRM) …

This paper presents a 1.5 to 10 Gb/s SATA/SAS/FC receiver in 65 nm CMOS. The multiple
constraints set by industry standards ask for a receiver architecture capable of …

A 7.5 Gb/s receiver has a 3-level DFE architecture to satisfy feedback timing requirements
for 10 post-cursor taps. The receiver includes a second-order CDR with partial-response …

This paper proposes a scalable and efficient frequency multiplication technique that
synthesizes a multi-phase clock with finely adjustable output taps. It uses a pulse injection …

<? Pub Dtl=""?> MOS-transistor-based current-mode logic (CML)-type (MCML) circuits in
high-speed circuit applications often operate as low-swing analog circuits rather than fully …

In this paper, the equalization techniques for high-speed interconnect transceivers are
discussed. Serial interconnect transceivers have been widely adopted for its high data …