irazor: Current-based error detection and correction scheme for pvt variation in 40-nm arm cortex-r4 processor

Y Zhang, M Khayatzadeh, K Yang… - IEEE Journal of Solid …, 2017 - ieeexplore.ieee.org
This paper presents iRazor, a lightweight error detection and correction approach, to
suppress the cycle time margin that is traditionally added to very large scale integration …

Voltage noise in multi-core processors: Empirical characterization and optimization opportunities

R Bertran, A Buyuktosunoglu, P Bose… - 2014 47th Annual …, 2014 - ieeexplore.ieee.org
Voltage noise characterization is an essential aspect of optimizing the shipped voltage of
high-end processor based systems. Voltage noise, ie Variations in the supply voltage due to …

Adaptive guardband scheduling to improve system-level efficiency of the POWER7+

Y Zu, CR Lefurgy, J Leng, M Halpern… - Proceedings of the 48th …, 2015 - dl.acm.org
The traditional guardbanding approach to ensure processor reliability is becoming obsolete
because it always over-provisions voltage and wastes a lot of energy. As a next-generation …

A 22 nm all-digital dynamically adaptive clock distribution for supply voltage droop tolerance

KA Bowman, C Tokunaga, T Karnik… - IEEE Journal of Solid …, 2013 - ieeexplore.ieee.org
An all-digital dynamically adaptive clock distribution mitigates the impact of high-frequency
supply voltage (V CC) droops on microprocessor performance and energy efficiency. The …

Margin elimination through timing error detection in a near-threshold enabled 32-bit microcontroller in 40-nm CMOS

H Reyserhove, W Dehaene - IEEE Journal of Solid-State …, 2018 - ieeexplore.ieee.org
This paper presents a near-threshold operating voltage timing error detecting 32-bit
microcontroller system. The lightweight in situ error detection and correction technique uses …

A 16-core voltage-stacked system with adaptive clocking and an integrated switched-capacitor dc–dc converter

SK Lee, T Tong, X Zhang, D Brooks… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
This paper presents a 16-core voltage-stacked system with adaptive frequency clocking
(AFClk) and a fully integrated voltage regulator that demonstrates efficient on-chip power …

An All-Digital, 1.92–7.32 mV/LSB, 0.5–2 GS/s Sample Rate, and 0-Latency Prediction Voltage Sensor With Dynamic PVT Calibration for Droop Detection and AVS …

Y Du, J Qian, Z Chen, W Shan - IEEE Transactions on Circuits …, 2023 - ieeexplore.ieee.org
The on-chip droop in processor may cause a severe voltage reduction resulting in a need for
high-speed and high-resolution on-chip voltage sensors. However, traditional voltage …

Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems

KA Bowman, JT Bridges, S Raina, YN Kolla… - US Patent …, 2016 - Google Patents
Automatic calibration circuits for operational calibration of critical-path time delays in
adaptive clock distribution sys tems, and related methods and systems, are disclosed. The …

5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep

C Tokunaga, JF Ryan, C Augustine… - … Solid-State Circuits …, 2014 - ieeexplore.ieee.org
The demand for high-performance graphics capability even in extremely power-constrained
platforms such as smartphones and tablets requires circuit techniques that scale from …

Aging-aware Adaptive Voltage Scaling in 22nm high-K/metal-gate tri-gate CMOS

M Cho, C Tokunaga, MM Khellah… - 2015 IEEE Custom …, 2015 - ieeexplore.ieee.org
Aging-aware Adaptive Voltage Scaling (AVS) can eliminate conventional flat voltage guard
band typically added to intrinsic chip V CC to account for transistor aging, therefore reducing …