Inkjet‐Printed and Deep‐UV‐Annealed YAlOx Dielectrics for High‐Performance IGZO Thin‐Film Transistors on Flexible Substrates
Recent developments in inkjet printing have proven it a viable method for low‐cost and large‐
area coating of oxide materials. The main drawback of this method is the common …
area coating of oxide materials. The main drawback of this method is the common …
High‐Performance Polycrystalline Silicon Thin‐Film Transistors without Source/Drain Doping by Utilizing Anisotropic Conductivity of Bridged‐Grain Lines
By utilizing anisotropic conductivity of bridged‐grain (BG) lines, a polycrystalline silicon (poly‐
Si) thin‐film transistor (TFT) without source/drain (S/D) doping is designed, simulated, and …
Si) thin‐film transistor (TFT) without source/drain (S/D) doping is designed, simulated, and …
Effect of grain boundary protrusion on electrical performance of low temperature polycrystalline silicon thin film transistors
We studied the impact of grain boundary (GB) protrusion on the electrical properties of low
temperature polycrystalline silicon thin film transistors. The analysis of atomic force …
temperature polycrystalline silicon thin film transistors. The analysis of atomic force …
NBTI mitigation by optimized HKMG thermal processing in a FinFET technology
B Ye, Y Gu, H Xu, C Tang, H Zhu… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
It has become more challenging to suppress the negative bias temperature instability (NBTI)
in advanced FinFET technology which is largely originated from the dielectric/channel …
in advanced FinFET technology which is largely originated from the dielectric/channel …
[HTML][HTML] Sub-kT/q subthreshold-slope using negative capacitance in low-temperature polycrystalline-silicon thin-film transistor
JH Park, GS Jang, HY Kim, KH Seok, HJ Chae… - Scientific reports, 2016 - nature.com
Realizing a low-temperature polycrystalline-silicon (LTPS) thin-film transistor (TFT) with sub-
kT/q subthreshold slope (SS) is significantly important to the development of next generation …
kT/q subthreshold slope (SS) is significantly important to the development of next generation …
Reduction of Parasitic Capacitance in Indium‐Gallium‐Zinc Oxide (a‐IGZO) Thin‐Film Transistors (TFTs) without Scarifying Drain Currents by Using Stripe‐Patterned …
A new device structure of oxide thin‐film transistor (TFT) having lower overlap capacitance
without scarifying the drain current is proposed. This can be used for high‐speed circuits …
without scarifying the drain current is proposed. This can be used for high‐speed circuits …
Junctionless nanosheet (3 nm) poly-Si TFT: Electrical characteristics and superior positive gate bias stress reliability
In this letter, a junctionless (JL) poly-Si thin-film transistor (TFT) with a 3-nm-thick nanosheet
channel is successfully fabricated using the low-temperature atomic level etching process …
channel is successfully fabricated using the low-temperature atomic level etching process …
Positive Gate-Bias Temperature Stability of RF-Sputtered Active-Layer Thin-Film Transistors
YS Tsai, JZ Chen - IEEE transactions on electron devices, 2011 - ieeexplore.ieee.org
This paper investigates the positive gate-bias temperature stability of RF-sputtered bottom-
gate Mg 0.05 Zn 0.95 O active-layer thin-film transistors (TFTs) annealed at 200° C for 5 h …
gate Mg 0.05 Zn 0.95 O active-layer thin-film transistors (TFTs) annealed at 200° C for 5 h …
Inhibiting the kink effect and hot-carrier stress degradation using dual-gate low-temperature poly-Si TFTs
HC Chen, SP Huang, YF Tu, CW Kuo… - IEEE Electron …, 2019 - ieeexplore.ieee.org
This study examines the appearance of a kink effect phenomenon in the ID-VD electrical
characteristics of low-temperature polycrystalline Si thin-film transistors (LTPS TFTs) after …
characteristics of low-temperature polycrystalline Si thin-film transistors (LTPS TFTs) after …
Exploring performance and reliability behavior of nanosheet channel thin-film transistors under independent dual gate bias operation
WCY Ma, CJ Su, KH Kao, YQ Chen… - ECS Journal of Solid …, 2023 - iopscience.iop.org
In this work, the polycrystalline-silicon (poly-Si) thin-film transistor with an independent dual-
gate (IDG) structure and ultra-thin nanosheet channel (∼ 4 nm) is fabricated to investigate …
gate (IDG) structure and ultra-thin nanosheet channel (∼ 4 nm) is fabricated to investigate …