Strain: A solution for higher carrier mobility in nanoscale MOSFETs
M Chu, Y Sun, U Aghoram… - Annual Review of …, 2009 - annualreviews.org
Metal-oxide-semiconductor field-effect transistors (MOSFETs) have shown impressive
performance improvements over the past 10 years by incorporating strained silicon (Si) …
performance improvements over the past 10 years by incorporating strained silicon (Si) …
Hole mobility in silicon inversion layers: Stress and surface orientation
G Sun, Y Sun, T Nishida, SE Thompson - Journal of Applied Physics, 2007 - pubs.aip.org
Hole transport in the p-type metal-oxide-semiconductor field-effect-transistor ( p-MOSFET)
inversion layer under arbitrary stress, surface, and channel orientation is investigated by …
inversion layer under arbitrary stress, surface, and channel orientation is investigated by …
DC and low frequency noise performances of SOI p-FinFETs at very low temperature
In this paper, DC and noise measurements on strained and unstrained SOI p-FinFETs were
performed at cryogenic temperatures (10 K) in order to evaluate the device performances …
performed at cryogenic temperatures (10 K) in order to evaluate the device performances …
Low frequency noise characterization in n-channel FinFETs
In this paper, the low frequency noise was studied from 100K up to room temperature in n-
channel triple-gate FinFET transistors fabricated on silicon on insulator (SOI) substrates. It …
channel triple-gate FinFET transistors fabricated on silicon on insulator (SOI) substrates. It …
Comparison of uniaxial wafer bending and contact-etch-stop-liner stress induced performance enhancement on double-gate FinFETs
S Suthram, MM Hussain, HR Harris… - IEEE electron device …, 2008 - ieeexplore.ieee.org
Longitudinal piezoresistance (pi) coefficients for n-and p-type double-gate (DG) FinFETs
with sidewall channels along (110) surface and (110) channel direction are measured via …
with sidewall channels along (110) surface and (110) channel direction are measured via …
Impact of strain and source/drain engineering on the low frequency noise behaviour in n-channel tri-gate FinFETs
W Guo, B Cretu, JM Routoure, R Carin, E Simoen… - Solid-State …, 2008 - Elsevier
The impact of strain-engineering on the low frequency of n-channel tri-gate FinFETs
fabricated on silicon on insulator (SOI) substrates noise is reported. The work is first focused …
fabricated on silicon on insulator (SOI) substrates noise is reported. The work is first focused …
In depth static and low-frequency noise characterization of n-channel FinFETs on SOI substrates at cryogenic temperature
The impact of cryogenic temperature operation (10 K) on the short channel effects and low
frequency noise was analysed on strained and unstrained n-channel FinFET transistors …
frequency noise was analysed on strained and unstrained n-channel FinFET transistors …
Zero-Temperature-Coefficient of planar and MuGFET SOI devices
The Zero Temperature Coefficient (ZTC) is investigated experimentally in planar and
standard/biaxially strained triple-gate nFinFETs fabricated on SOI wafers. In this work a …
standard/biaxially strained triple-gate nFinFETs fabricated on SOI wafers. In this work a …
Analog performance of gate-source/drain underlap triple-gate SOI nMOSFET
SD Santos, T Nicoletti, JA Martino - ECS Transactions, 2011 - iopscience.iop.org
The electrical characteristics of triple-gate SOI nMOSFET with gate-source/drain underlap
are studied in this paper, focusing on the main analog parameters through 3D numerical …
are studied in this paper, focusing on the main analog parameters through 3D numerical …
Improved analytical model for ZTC bias point for strained tri-gates FinFETs
The zero temperature coefficient (ZTC) is investigated experimentally in standard and
biaxially strained Tri-gate nFinFETs fabricated on SOI wafers. In this work an improved …
biaxially strained Tri-gate nFinFETs fabricated on SOI wafers. In this work an improved …