Selecting a set of features which is optimal for a given task is a problem which plays an
important role in wide variety of contexts including pattern recognition, adaptive control and …

As technology scales to 32 nm and functional frequency and density continue to rise, PSN
effects, which can reduce a circuit's noise immunity and could lead to failures, pose new …

In this paper, some of the most practically interesting full adder topologies are analyzed in
terms of their delay dependence on the supply voltage fluctuations, which are a major …

Excessive power supply noise can affect path delay and cause overkill during delay test.
This paper presents low-cost noise models for fast power supply noise analysis and timing …

Power supply noise management continues to be a challenge with the scaling of CMOS
technologies. Use of on-chip decoupling capacitors (decaps) is the most common noise …

As technology scales, gate sensitivity to noise increases due to supply voltage scaling and
limited scaling of the voltage threshold. As a result, power supply noise plays a greater role …

As technology shrinks, gate sensitivity to noise increases due to supply voltage scaling and
limited scaling of the voltage threshold. As a result, power supply noise (PSN) plays a …

This paper presents a gate delay estimation method that takes into account dynamic power
supply noise. We review STA based on static IR-drop analysis and a conventional method …

This paper proposes an approach to cope with temporal power/ground voltage fluctuation
for static timing analysis. The proposed approach replaces temporal noise with an …

Excessive power supply noise can lead to overkill during delay test. A static test vector
compaction solution is described to prevent such overkill. Low-cost power supply noise …