MC Williamson, EA Lee - Conference Record of The Thirtieth …, 1996 - ieeexplore.ieee.org
We detail a method for the partitioning of a single application specified in synchronous dataflow (SDF) into multiple independently-synthesizable, communicating VHDL hardware …
This dissertation describes an approach to digital hardware design for embedded signal processing systems that addresses synthesis, simulation, and interactive design. The …
M Mottaghi-Kashtiban, S Farazi… - … Symposium on Signal …, 2006 - ieeexplore.ieee.org
This paper presents the optimum and minimum order structures for sample rate conversion from 44.1 KHz compact disc (CD) to 48 KHz digital audio tape (DAT) and from DAT to CD …
W Sung, S Ha - IEICE transactions on fundamentals of electronics …, 1998 - search.ieice.org
Hardware software codesign using various hardware and software implementation possibilities requires a cosimulation environment which has both flexibility and efficiency. In …
In this paper we propose a new communication synthesis approach targeting systems with sequential communication media (SCM). Since SCMs require that the reading sequence …
HN El-Ghoroury - US Patent 6,938,237, 2005 - Google Patents
According to one embodiment of the present invention, a method and system for VLSI hardware design and synthesis is provided in which components provided by a …
W Sung, S Ha - Proceedings of 1998 Asia and South Pacific …, 1998 - ieeexplore.ieee.org
A hardware software cosimulation environment is developed using the backplane approach. This paper defines the backplane protocol for communication and synchronization between …
W Sung, M Oh, C Im, S Ha - in Proc. of International Conference of VLSI …, 1997 - Citeseer
A concurrent hardware software codesign environment, PeaCE, is presented in this paper. PeaCE provides the designer with an environment in which the designer can design …
W Sung, M Oh, S Ha - Proceedings of APCHDL, 1997 - researchgate.net
To perform cosimulation, an interface design of VHDL simulation is needed. This interface is responsible for communicating packets between any VHDL simulator and the cosimulation …