Review–Silicon Based ISFETs: Architecture, Fabrication Process, Sensing Membrane, and Spatial Variation

A Gupta, S Sharma, R Goswami - ECS Journal of Solid State …, 2024 - iopscience.iop.org
The main characteristics of a good pH detecting system are higher sensitivity, ease of
manufacturing process, and a micro-system. Ion sensitive field effect transistors (ISFETs) …

A method for reduction of off state leakage current in symmetric DG JLT

KCD Sarma, S Sharma - Engineering Research Express, 2019 - iopscience.iop.org
A novel method for reduction of off state leakage current in a symmetric double gate
junctionless transistor (DG JLT) is presented in this paper. In this technique a layer of …

Study of performance evaluation of various characteristics of a single phase full bridge inverter circuit using surrounded channel junctionless field effect transistor

N Das, KCD Sarma - Discover Electronics, 2024 - Springer
This paper reports the characteristics study of a single phase full bridge power electronic
inverter circuit with a new type of technology namely surrounded channel junctionless field …

Analysis of an Approximated Model for the Depletion Region Width of Planar Junctionless Transistors

A Nowbahari, A Roy, M Nadeem Akram, L Marchetti - Electronics, 2019 - mdpi.com
In this paper, we investigate the accuracy of the approximated analytical model currently
utilized, by many researchers, to describe the depletion region width in planar junctionless …

[PDF][PDF] Discover Electronics

N Das, KCD Sarma - 2024 - researchgate.net
This paper reports the characteristics study of a single phase full bridge power electronic
inverter circuit with a new type of technology namely surrounded channel junctionless field …

An Analysis of Surface Potential and Drain Current of a Split-Gate Junctionless Transistor Using 3-D TCAD

S Keithellakpam, N Bora - … on Intelligent Computing Techniques For Smart …, 2023 - Springer
In this paper, a split-gate junctionless transistor (SG-JLT) is modeled, and the simulation is
carried out. The I–V characteristic of the SG-JLT was compared and analyzed with the …

A Simulation Study of Raised Source Drain Double Gate Junctionless Field Effect Transistor

KCD Sarma, D Deka… - 2023 4th International …, 2023 - ieeexplore.ieee.org
This paper presents a simulation-based study on a raised source drain Junctionless Field
Effect Transistor (JLFET). The electrical characteristics of a JLFET structure which is having …

[PDF][PDF] Study on performance Evaluation of CMOS Inverter using Surrounded channel Junctionless Field Effect Transistor

N Das, KCD Sarma - 2023 - assets-eu.researchsquare.com
The paper present here analyses the modeling and performance of CMOS inverters using
surrounded channel Junction less field effect transistor (SCJLFET). A mathematical model …

Channel Potential Modelling of Surrounded Channel Junction Less Field Effect Transistor

N Das, KC Deva Sarma - Journal of Nanoelectronics and …, 2022 - ingentaconnect.com
An analytical model for potential in channel region is obtained for a Surrounded channel
junction-less field effect transistor. Two dimensional Poisson's equation has been solved to …

An analytical approach for drain current modelling of a symmetric double gate junctionless transistor

S Sharma, KCD Sarma - Journal of Nanoelectronics and …, 2018 - ingentaconnect.com
In this paper a fully analytical approach for drain current modelling of a symmetric double
gate junctionless transistor is presented. In this approach the channel is divided into a …