A 28-nm FD-SOI 115-fs jitter PLL-based LO system for 24–30-GHz sliding-IF 5G transceivers

S Ek, T Påhlsson, C Elgaard, A Carlsson… - IEEE Journal of Solid …, 2018 - ieeexplore.ieee.org
A system for local oscillator (LO) signal generation in 5G millimeter-wave (mmW) multi-
antenna transceivers is presented. The system is modular with one phase locked loop (PLL) …

A 1.9–3.8 GHz Fractional-N PLL Frequency Synthesizer With Fast Auto-Calibration of Loop Bandwidth and VCO Frequency

J Shin, H Shin - IEEE Journal of Solid-State Circuits, 2012 - ieeexplore.ieee.org
A fast and high-precision all-digital automatic calibration circuit that is highly suited for ΔΣ
fractional-N synthesizers is designed to achieve a constant loop bandwidth and fast lock …

A PVT-robust and low-jitter ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge …

S Choi, S Yoo, Y Lim, J Choi - IEEE Journal of Solid-State …, 2016 - ieeexplore.ieee.org
A low-jitter, ring-type voltage-controlled oscillator (VCO)-based injection-locked clock
multiplier (ILCM) with a continuous frequency-tracking loop (FTL) for process …

A fractional-N divider-less phase-locked loop with a subsampling phase detector

WS Chang, PC Huang, TC Lee - IEEE Journal of Solid-State …, 2014 - ieeexplore.ieee.org
A low-noise divider-less PLL, employing a subsampling locked loop, samples the VCO
output by a digital pulse-width modulator (DPWM) to perform fractional-N operation. The …

A 12-/13.56-MHz Crystal Oscillator With Binary-Search-Assisted Two-Step Injection Achieving 5.0-nJ Startup Energy and 45.8-s Startup Time

H Li, KM Lei, RP Martins, PI Mak - IEEE Journal of Solid-State …, 2023 - ieeexplore.ieee.org
This article reports a 12-/13.56-MHz fast-and-energy-efficient startup crystal oscillator (XO)
featuring a binary-search-assisted two-step injection technique for ultralow-power duty …

Reconfigurable all-band RF CMOS transceiver for GPS/GLONASS/Galileo/Beidou with digitally assisted calibration

S Li, J Li, X Gu, H Wang, C Li, J Wu… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
This paper presents a fully integrated reconfigurable all-band RF transceiver for
GPS/GLONASS/Galileo/Beidou in 55-nm CMOS. The transceiver incorporates three low-IF …

A 0.045-to 2.5-GHz frequency synthesizer with TDC-based AFC and phase switching multi-modulus divider

A Hu, D Liu, K Zhang, L Liu… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
A 0.045-to 2.5-GHz wideband frequency synthesizer (FS) employing time-to-digital converter
(TDC) based automatic frequency calibration (AFC) method and phase switching (PS) multi …

A low-power fast-settling bond-wire frequency synthesizer with a dynamic-bandwidth scheme

B Zhao, Y Lian, H Yang - … on Circuits and Systems I: Regular …, 2013 - ieeexplore.ieee.org
This paper presents a low-power fast-settling phase-locked loop (PLL) frequency
synthesizer working at 1.72–1.74 GHz for a 100 kb/s Gaussian frequency shift keying …

A 0.4–6-GHz frequency synthesizer using dual-mode VCO for software-defined radio

J Zhou, W Li, D Huang, C Lian, N Li… - IEEE transactions on …, 2012 - ieeexplore.ieee.org
This paper presents a dual-mode voltage-controlled oscillator (DMVCO) and a DMVCO-
based wideband frequency synthesizer for software-defined radio applications. The DMVCO …

Single sine wave parameters estimation method based on four equally spaced samples

DN Vizireanu, SV Halunga - International Journal of Electronics, 2011 - Taylor & Francis
This article presents a general method to determine all the parameters of a single wave
carrier signal ie the frequency, phase, amplitude and DC component, based on four different …