N Kandpal, A Singh, A Agarwal - AEU-International Journal of Electronics …, 2023 - Elsevier
This paper presents variable resolution SAR ADC with digitally implemented Bit enhancement logic. Unlike conventional approaches, this work avoids complex hardware …
PR Castaneda-Avina, E Tlelo-Cuautle… - AIMS …, 2022 - aimspress.com
Real applications of integrated circuits (ICs) require satisfying strong target specifications, which challenge is focused on trading off specifications that are in conflict, ie improving one …
N Kandpal, A Singh, A Agarwal - International Journal of Circuit …, 2024 - Wiley Online Library
This paper presents an artificially intelligent Flash ADC with enhanced resolution from 4 to 10 bits. Unlike conventional approaches, this artificial intelligence (AI)‐based architecture …
X Qian, W Jiang, MJ Deen - 2022 IEEE International IOT …, 2022 - ieeexplore.ieee.org
Accurate photon detection probability (PDP) modeling is important for the optimized design of single-photon avalanche diodes (SPADs) using modern standard CMOS technologies. To …
R Kumar, R Nagulapalli… - Journal of Circuits …, 2023 - World Scientific
Phase Locked Loop (PLL) is an on-chip clock generator for timing-centric electronic systems. Voltage Controlled Oscillator (VCO) is the key element for high-performance PLLs …