Quantifiable assurance: from IPs to platforms
Hardware vulnerabilities are generally considered more difficult to fix than software ones
because they are persistent after fabrication. Thus, it is crucial to assess the security and fix …
because they are persistent after fabrication. Thus, it is crucial to assess the security and fix …
Quantifiable Assurance in Hardware
M Tehranipoor, K Zamiri Azar, N Asadizanjani… - Hardware Security: A …, 2024 - Springer
Hardware vulnerabilities are generally considered more difficult to fix than software ones
because they are persistent after fabrication. Thus, it is crucial to assess the security and fix …
because they are persistent after fabrication. Thus, it is crucial to assess the security and fix …
Test Adapted Shielding by a Multipurpose Crosstalk Avoidance Scheme
M Akhsham, A Seyedolhosseini… - 2019 IEEE European …, 2019 - ieeexplore.ieee.org
Crosstalk noise due to the electromagnetic coupling between wires adversely affects VLSI
circuit performance. This makes interconnect testing an important issue in reliability …
circuit performance. This makes interconnect testing an important issue in reliability …
[HTML][HTML] 温度和频率对互连线信号完整性的影响
魏建军， 王振源， 陈付龙， 刘乃安， 李晓辉， 韦娟 - 哈尔滨工程大学学报, 2019 - html.rhhz.net
针对VLSI 中的互连线信号完整性问题, 研究温度和频率对电阻, 电感和电容的影响.
在温度和频率的作用下, 采用多节RLC 模型, 分别探讨温度和频率对互连线电学特性的影响 …
在温度和频率的作用下, 采用多节RLC 模型, 分别探讨温度和频率对互连线电学特性的影响 …
Design and Implementation of Crosstalk Noise Avoidance by using Advanced Test Adapted Shielding for high speed vlsi circuits
B Obulesu, KV Raju, PS Sumanth… - … on Emerging Smart …, 2023 - ieeexplore.ieee.org
The Crosstalk noise is existing in VLSI circuits because of the electromagnetic coupling in
between the wires unfriendly, it affects the VLSI circuits accurate performance. This makes …
between the wires unfriendly, it affects the VLSI circuits accurate performance. This makes …
Integrating an Interconnect BIST with Crosstalk Avoidance Hardware
M Akhsham, Z Navabi - … Symposium on On-Line Testing and …, 2021 - ieeexplore.ieee.org
An online interconnect BIST for detecting and avoiding interconnect faults is proposed in this
paper. This BIST structure is built upon a new shielding method, the required hardware of …
paper. This BIST structure is built upon a new shielding method, the required hardware of …
Off-chip bus power minimization using serialization with cache-based encoding
The data bus is a major component of high power consumption in small process high-
performance systems and in systems-on-chip (SoC) design. This paper presents an analysis …
performance systems and in systems-on-chip (SoC) design. This paper presents an analysis …