A general model of phase-locked loops (PLLs) is derived which incorporates the influence of
divide value variations. The proposed model allows straightforward noise and dynamic …

A digital compensation method and key circuits are presented that allow fractional-N
synthesizers to be modulated at data rates greatly exceeding their bandwidth. Using this …

The design of a 2.4-GHz fully integrated ΣΔ fractional-N frequency synthesizer in a 0.35-μm
CMOS process is presented. The design focuses on the prescaler and the loop filter, which …

The increasingly demanding performance requirements of communications systems, as well
as problems posed by the continued scaling of silicon technology, present numerous …

This paper describes a 1.8-GHz self-calibrated phase-locked loop (PLL) implemented in
0.35-/spl mu/m CMOS technology. The PLL operates as an edge-combining type fractional …

A hybrid analog-digital quarter-rate clock and data recovery circuit (CDR) that achieves a
wide-tracking range and excellent frequency and phase tracking resolution is presented in …

Since/spl Delta//spl Sigma/Fractional-N synthesis is becoming a popular path to synthesizer
integration, thorough analysis is mandatory to uncover its pitfalls. Two generic analysis …

A 5.3-GHz low-voltage CMOS frequency divider whose modulus can be varied from 220 to
224 is presented. Programmability is achieved by switching between different output phases …

A fractional-N phase-locked loop (PLL) serves as a Gaussian minimum-shift keying (GMSK)
transmitter and a receive frequency synthesizer for GSM. The entire transmitter/synthesizer …

A novel and useful apparatus for and method of improving the quantization resolution of a
time to digital converter in a digital PLL using noise shaping. The TDC quantization noise …