We reduce cache supply voltage below the normally acceptable VDDMIN, in order to
improve overall many-core system energy efficiency. Based on the observation that cache …

Aggressive voltage scaling to reduce energy consumption in Multicore causes exponential
cell failures in SRAM. Last-level-cache (LLC), the major contender of chip area, exhibits …

Power dissipation in Chip Multiprocessors (CMPs) has been addressed by Dynamic Voltage
and Frequency Scaling (DVFS). But uncontrolled reduction of voltage supply results in …

With increased number of cores in Multicore Chips, power consumption raises. Voltage
scaling is applied largely but it causes cell failure in cache. For that, various techniques for …

Dynamic voltage and frequency scaling puts threats to reliability in Chip Multiprocessors
(CMPs). Cache being the most susceptible to faults, the fault tolerance techniques are …

On top of the wear-out failures and external particle interventions, voltage scaling to mitigate
the power consumption in multiprocessor makes cache more vulnerable to cell failures. For …

Abstract Dynamic Voltage and Frequency Scaling (DVFS) for reducing power dissipation in
Multicore Chips causes cell failure in Cache Memory. Various fault tolerance techniques …

Power density is currently the primary design constraint across most computing segments
and the main performance limiting factor. For years, industry has kept power density …

Aggressive technology scaling in the nano-scale regime makes chips more susceptible to
failures. This causes multiple reliability challenges in the design of modern chips, including …

[BCHL19, BCEP12, BM13, CP13a, CDBB24, CKGN14, CC14, CBH22a, CBH22b, CP13b,
DV13, DSD12, Edi13, FM12, GV21b, Goe14, GP07, HCK+08, HTLC10, Hüb13, JB02, JB03 …