Digital radio-over-fiber system with multi-pulse Manchester encoding-assisted delta-sigma modulation
S Jang, B Park, S Hong - Optics Express, 2017 - opg.optica.org
Two∆ Σ-modulated digital radio-over-fiber (DRoF) transmission systems that employ a multi-
pulse Manchester encoder are proposed and experimentally evaluated. With a two-step …
pulse Manchester encoder are proposed and experimentally evaluated. With a two-step …
Multilevel half-rate phase detector for clock and data recovery circuits
In this brief, a half-rate (HR) bang-bang (BB) phase detector (PD) with multiple decision
levels is proposed for clock and data recovery (CDR) circuits. The combination allows the …
levels is proposed for clock and data recovery (CDR) circuits. The combination allows the …
An ultra-high speed monolithic clock recovery circuit in 0.2-µm GaAs process
L Tang, Z Wang, Y Qiu, C Zhang, J Xu - Analog Integrated Circuits and …, 2015 - Springer
This paper presents a 37 Gb/s phase locked-loop (PLL)-type clock recovery (CR) circuit
designed and fabricated in 0.2-µm GaAs PHEMT process. The resonator of the modified LC …
designed and fabricated in 0.2-µm GaAs PHEMT process. The resonator of the modified LC …
Burst mode receiver for GPON
This paper presents the design, implementation and test results of Burst Mode Receiver
(BMRx) for Gigabit Passive Optical Networks (GPON) at 2.488 Gb/s. Unlike the continuous …
(BMRx) for Gigabit Passive Optical Networks (GPON) at 2.488 Gb/s. Unlike the continuous …
A 0.5-to-4 Gbps continuous-rate clock and data recovery circuit with bidirectional frequency detection
This paper presents a continuous-rate clock and data recovery circuit with bidirectional
frequency detection. The proposed frequency detection mechanism skillfully combines …
frequency detection. The proposed frequency detection mechanism skillfully combines …
A 2.5-Gb/s fully-integrated, low-power clock and recovery circuit in 0.18-μm CMOS
Z Changchun, W Zhigong, S Si… - Journal of …, 2010 - iopscience.iop.org
Based on the devised system-level design methodology, a 2.5-Gb/s monolithic bang-bang
phase-locked clock and data recovery (CDR) circuit has been designed and fabricated in …
phase-locked clock and data recovery (CDR) circuit has been designed and fabricated in …