Modern mobile GPUs integrate an increasing number of shader cores to speedup the
execution of graphics workloads. Each core integrates a private Texture Cache to apply …

Wire delays and leakage energy consumption are both growing problems in designing large
on-chip caches. Nonuniform cache architecture (NUCA) is a wire-delay aware design …

The last level on-chip cache (LLC) is becoming bigger and more complex to effectively
support the various localities coming from multiple cores and threads running concurrently in …

Improvements in semiconductor nanotechnology made chip multiprocessors the reference
architecture for high-performance microprocessors. CMPs usually adopt large Last-Level …

In this paper, we propose a new edge-based text verification approach for video. Based on
the investigation of the relation between candidate blocks and their neighbor areas, the …

Chip Multiprocessor (CMP) systems have become the reference architecture for designing
micro-processors, thanks to the improvements in semiconductor nanotechnology that have …

Wire delays and leakage energy consumption are both growing problems in the design of
large on chip caches built in deep submicron technologies. D-NUCA caches (Dynamic …

Improvements in semiconductor nanotechnology have continuously provided a crescent
number of faster and smaller per-chip transistors. Consequent classical techniques for …

This paper proposes a novel indoor localization system, specifically designed for use in
healthcare environments. The challenge for this indoor localization project is to decide in …

It is essential to accurately estimate the working set size (WSS) of an application for various
optimizations such as to partition cache among virtual machines or reduce leakage power …