A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk
Time-interleaved (TI) analog-to-digital converters (ADCs) are an established architecture,
but fundamental problems still exist that prevent replicating the performance of each sub …
but fundamental problems still exist that prevent replicating the performance of each sub …
A 250-MS/s 9.9-ENOB 80.7 dB-SFDR Top-Plate Input SAR ADC With Charge Linearization
This brief presents a linearity enhancement method, named charge linearization technique
(CLT), for top-plate input successive approximation register (SAR) data converters. The …
(CLT), for top-plate input successive approximation register (SAR) data converters. The …
A 12-bit 50MS/s SAR ADC with non-binary split capacitive DAC in 40nm CMOS
X Hou, Z Duan, Z Huang, B Wu, D Zhao… - IEICE Electronics …, 2024 - jstage.jst.go.jp
A 12-bit successive approximation register-based analog-todigital converter (SAR ADC) with
non-binary search technology is introduced. By embedding redundant weights in the branch …
non-binary search technology is introduced. By embedding redundant weights in the branch …
A 150 MS/s, 10 bit SAR ADC Featuring a Modified Quasi-Monotonic Switching Scheme
V Spinogatti, C Bocciarelli, L Eusebio… - … 19th Conference on …, 2024 - ieeexplore.ieee.org
This work proposes a novel switching algorithm for capacitive digital-to-analog converters
(CDAC) in successive approximation register (SAR) analog-to-digital converters (ADC). The …
(CDAC) in successive approximation register (SAR) analog-to-digital converters (ADC). The …