[图书][B] VLSI test principles and architectures: design for testability
This book is a comprehensive guide to new DFT methods that will show the readers how to
design a testable and quality product, drive down test cost, improve product quality and …
design a testable and quality product, drive down test cost, improve product quality and …
Embedded deterministic test
J Rajski, J Tyszer, M Kassab… - IEEE transactions on …, 2004 - ieeexplore.ieee.org
This paper presents a novel test-data volume-compression methodology called the
embedded deterministic test (EDT), which reduces manufacturing test cost by providing one …
embedded deterministic test (EDT), which reduces manufacturing test cost by providing one …
Built-in self-test (BIST) methods for MEMS: A review
A novel taxonomy of built-in self-test (BIST) methods is presented for the testing of micro-
electro-mechanical systems (MEMS). With MEMS testing representing 50% of the total costs …
electro-mechanical systems (MEMS). With MEMS testing representing 50% of the total costs …
[图书][B] System-on-chip test architectures: nanometer design for testability
LT Wang, CE Stroud, NA Touba - 2010 - books.google.com
Modern electronics testing has a legacy of more than 40 years. The introduction of new
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
Embedded deterministic test for low cost manufacturing test
J Rajski, J Tyszer, M Kassab… - Proceedings …, 2002 - ieeexplore.ieee.org
This paper introduces embedded deterministic test (EDT) technology, which reduces
manufacturing test cost by providing one to two orders of magnitude reduction in scan test …
manufacturing test cost by providing one to two orders of magnitude reduction in scan test …
OPMISR: The foundation for compressed ATPG vectors
C Barnhart, V Brunkhorst, F Distler… - … 2001 (Cat. No …, 2001 - ieeexplore.ieee.org
Rapid increases in the wire-able gate counts of ASICs stress existing manufacturing test
equipment in terms of test data volume and test capacity. Techniques are presented in this …
equipment in terms of test data volume and test capacity. Techniques are presented in this …
An efficient test vector compression scheme using selective Huffman coding
A Jas, J Ghosh-Dastidar, ME Ng… - IEEE transactions on …, 2003 - ieeexplore.ieee.org
This paper presents a compression/decompression scheme based on selective Huffman
coding for reducing the amount of test data that must be stored on a tester and transferred to …
coding for reducing the amount of test data that must be stored on a tester and transferred to …
Variable-length input Huffman coding for system-on-a-chip test
PT Gonciari, BM Al-Hashimi… - IEEE Transactions on …, 2003 - ieeexplore.ieee.org
This paper presents a new compression method for embedded core-based system-on-a-
chip test. In addition to the new compression method, this paper analyzes the three test data …
chip test. In addition to the new compression method, this paper analyzes the three test data …
Reducing test data volume using LFSR reseeding with seed compression
CV Krishna, NA Touba - Proceedings. International Test …, 2002 - ieeexplore.ieee.org
A new lossless test vector compression scheme is presented which combines linear
feedback shift register (LFSR) reseeding and statistical coding in a powerful way. Test …
feedback shift register (LFSR) reseeding and statistical coding in a powerful way. Test …
Extending opmisr beyond 10/spl times/scan test efficiency
C Barnhart, V Brunkhorst, F Distler… - IEEE Design & Test …, 2002 - ieeexplore.ieee.org
Extending OPMISR beyond 10/spl times/ scan test efficiency Page 1 65 0740-7475/02/$17.00 ©
2002 IEEE September–October 2002 SCAN-BASED LOGIC TESTING using auto- matic …
2002 IEEE September–October 2002 SCAN-BASED LOGIC TESTING using auto- matic …