This paper presents a high-speed low-power cryogenic CMOS two-stage dynamic
comparator for SAR ADC. The pre-amplifier uses the dynamic bias technique to save power …

This study presents a fully differential dynamic comparator with low kickback noise, an effect
caused by voltage variations in the regeneration nodes of these types of circuit. Given their …

Nowadays, in all modern electronic devices a low voltage with high speed comparator plays
an important role in overall performance of the systems. This paper describes the …

In this paper, a low‐power 10‐bit 15‐MS/s opamp‐less pipelined analog‐to‐digital
converter (ADC) has been proposed. The circuit is comprised of eight 1.5‐bit/stage MDACs …

This paper presents a high-speed low-power two-stage dynamic comparator for SAR ADC.
The pre-amplifier of the proposed comparator uses the dynamic bias technique to save …

The power consumption of chips has emerged as a major concern with the increased
integration of analog circuitry. This work focuses on a two‐stage comparator based on a …

This paper presents an asynchronous hybrid Flash-SAR ADC for low energy radio
applications. A new technique is introduced for decreasing the number of comparators of the …

Contemporarily, Analog-to-digital converter (ADC) is widely used in our daily life, eg and the
function of ADC is to convert input analog signals into output digital signals. With the …

This paper presents a high-speed voltage based on Strong-Arm comparator with a MOM
capacitor array. The comparator increases the discharge path of output node to improve the …

This paper introduces a novel structure for the comparator of analog-to-digital convertor with
built-in threshold. Thus the resistor string can be eliminated. The proposed comparator is …