A 2 GHz 244 fs-resolution 1.2 ps-peak-INL edge interpolator-based digital-to-time converter in 28 nm CMOS

S Sievert, O Degani, A Ben-Bassat… - IEEE Journal of Solid …, 2016 - ieeexplore.ieee.org
This paper presents a 2 GHz digital-to-time converter (DTC) with 244 fs time resolution. The
DTC consists of a multi-modulus divider (MMD) and a phase interpolator (PI) as coarse and …

A 31- W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS

P Chen, F Zhang, Z Zong, S Hu… - IEEE Journal of Solid …, 2019 - ieeexplore.ieee.org
This article proposes a power-efficient highly linear capacitor-array-based digital-to-time
converter (DTC) using a charge redistribution constant-slope approach. A fringe-capacitor …

Mismatch analysis of DTCs with an improved BIST-TDC in 28-nm CMOS

P Chen, J Yin, F Zhang, PI Mak… - … on Circuits and …, 2021 - ieeexplore.ieee.org
Nonlinearity of a digital-to-time converter (DTC) is pivotal to spur performance in DTC-based
all-digital phase-locked-loops (ADPLL). In this paper, we characterize and analyze the …

A Fast Settling Fractional- DPLL With Loop-Order Switching

P Paliwal, V Yadav, Z Ali… - IEEE Transactions on Very …, 2019 - ieeexplore.ieee.org
The enhancement in the settling response of frequency synthesizers would open up
prospects for new applications such as spread spectra and frequency hopping systems …

An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-Order Loop

P Chen, X Huang, Y Chen, L Wu… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
To characterize an on-chip programmable delay in a low-cost and high-resolution manner, a
built-in self-test based on a first-order time-to-digital converter with self-calibration is …

A 1 V 10-bit highly linear and monotonic digital-to-time converter with 0.066-LSB DNL utilizing a glitch-free dual reset method and switchable supply regulation …

I Jung, S Bae, S Lee, M Lee - Analog Integrated Circuits and Signal …, 2022 - Springer
This paper describes a 10-bit digital-to-time converter (DTC) utilizing the glitch-free dual
reset method and switchable supply regulation scheme for high linearity regardless of …

Self-Calibrating Digital-to-Time Converter in CMOS for Advanced Control in Smart Gate Drivers

ES Bocholt, L Rolff, R Wunderlich… - 2019 17th IEEE …, 2019 - ieeexplore.ieee.org
Time resolution is a major issue for smart gate drivers. These offer the potential to
significantly increase switching performance of power switches. The proposed self …

Low power digitally controlled oscillator for IoT applications

MB Moreira - 2021 - lume.ufrgs.br
This work is focused on the design of a Low Power CMOS DCO for IEEE 802.11 ah in IoT
applications. The design methodology is based on the Unified current-control model (UICM) …

Development of analytical behavioral models for digitally controlled edge interpolator (DCEI) based digital-to-time converter (DTC) circuits

S Sievert - 2017 - mediatum.ub.tum.de
Digital-to-time converter (DTC) circuits enable various applications in the area of frequency
synthesis. Phase interpolator (PI) circuits are popular DTC fine tuning elements, however …

A 10 Bit Phase-Interpolator-Based Digital-to-Phase Converter for Accurate Time Synchronization in Ethernet Applications

S Buhr, C Hoyer, M Kreißig… - 2020 27th IEEE …, 2020 - ieeexplore.ieee.org
This work presents a 10 Bit digital-to-phase converter (DPC), for usage within an accurate
time synchronization via Ethernet with a nominal frequency of 125 MHz. It is based on a 16 …