Alternate Path μ-op Cache Prefetching

S Singh, A Perais, A Jimborean… - 2024 ACM/IEEE 51st …, 2024 - ieeexplore.ieee.org
Datacenter applications are well-known for their large code footprints. This has caused
frontend design to evolve by implementing decoupled fetching and large prediction …

Enabling branch-mispredict level parallelism by selectively flushing instructions

S Eyerman, W Heirman, S Van den Steen… - MICRO-54: 54th Annual …, 2021 - dl.acm.org
Conventionally, branch mispredictions are resolved by flushing wrongly speculated
instructions from the reorder buffer and refetching instructions along the correct path …

Auto-predication of critical branches

A Chauhan, J Gaur, Z Sperber, F Sala… - 2020 ACM/IEEE 47th …, 2020 - ieeexplore.ieee.org
Advancements in branch predictors have allowed modern processors to aggressively
speculate and gain significant performance with every generation of increasing out-of-order …

Breaking In-Order Branch Miss Recovery

S Eyerman, W Heirman… - IEEE Computer …, 2020 - ieeexplore.ieee.org
Despite very accurate branch predictors, branch misses remain an important source of
performance limiters, especially for irregular applications. To ensure in-order commit, branch …

An improvement in the convergence of superscalar processors

D Spasov - 2020 43rd International Convention on Information …, 2020 - ieeexplore.ieee.org
Modern processors include reservation stations to host instructions that are waiting to be
sent to the execution units. Responsive to exception event, instructions in reservation …

A Circuit for Flushing Instructions from Reservation Stations in Microprocessors

D Spasov - ICT Innovations 2020. Machine Learning and …, 2020 - Springer
Modern processors include reservation stations to host instructions that are waiting to be
sent to the execution units. Instructions in reservation stations may be waiting for source …