A PEEC-Based Fast Direct Solver for Interconnect L&R Extraction
P Wang, Y Chen, X Que, J Hu - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
A fast direct solver based on the partial element equivalent circuit is proposed for extracting
the parasitic inductance and resistance of high-speed interconnects in free space. By …
the parasitic inductance and resistance of high-speed interconnects in free space. By …
Nonorthogonal 2.5-D PEEC for power integrity analysis of package-board geometries
BP Nayak, SR Vedicherla… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
Design of the power ground layout of a multilayered printed circuit board (PCB) is crucial for
low noise and stable power supply. 2.5-D tools are better suited for early stage power …
low noise and stable power supply. 2.5-D tools are better suited for early stage power …