This brief presents a differentially terminated CML transmitter with a self-calibration scheme
based on time-domain reflectometry for preemphasis strength control. Without any …

Clock is one of the most important signals in a chip. However, due to changes in materials,
packaging, process, temperature, and other manufacturing processes, there may be …

An open‐loop per‐pin skew compensation with lock fault detection is presented. The
proposed circuit employs an open‐loop reference selector, a two‐stage open‐loop delay …

Growing computational demand and proliferation of cloud computing has placed high-speed
serial links at the center stage. Due to saturating energy efficiency improvements over the …

High speed serial links are critical components for addressing the growing demand for I/O
bandwidth in next-generation computing applications, such as many-core systems …

Abstract A 1.2‐Gbps GDDR3 physical layer (PHY) circuit for flat panel displays is presented.
To reduce the channel skew and to make the clock robust against power supply noise, an …

A self-calibrating per-pin phase adjuster, which does not require any feedback from the
slave chip and a multi-phase clock in the master and slave chips, is proposed for a high …