With scaling of device dimensions, microscopic variations in number and location of dopant
atoms in the channel region of the device induce increasingly limiting electrical deviations in …

This paper presents a new fault-tolerance technique for cache memories. Current fault-
tolerance techniques for caches are limited either by the number of faults that can be …

As process technology continues to shrink, a large number of bitcells in on-chip caches is
expected to be faulty. The number of defective cells varies from die-to-die, wafer-to-wafer …

Technology scaling leads to significant faulty bit rates in on-chip caches. In this work, we
propose a methodology to mitigate the impact of defective bits (due to permanent faults) in …

Reducing the supply voltage in today′ s process technologies introduces significant
reliability challenges for on-chip SRAM arrays. As a reaction, many Cache Fault-Tolerance …

Yield improvement through exploiting fault-free sections of defective chips is a well-known
technique (Koren and Singh (1990) and Stapper et al.(1980)). The idea is to partition the …

Power dissipation in Chip Multiprocessors (CMPs) has been addressed by Dynamic Voltage
and Frequency Scaling (DVFS). But uncontrolled reduction of voltage supply results in …

Yield enhancement through the acceptance of partially good chips is a well-known
technique. In this paper, we derive a yield model for single-chip VLSI processors with …

As the technology continuous to shrink, power consumption appears to be the main design
parameter. Operation on low voltage negatively affects mainly the operation of on-chip …

In this work, we propose architectural solutions to cope with permanent faults in cache
memories. The approach uses a FIFO and a redundant cache to detect and tolerate …