Photosensitivity Performance of a Gate-Oxide-Stack Intended Source FDSOI Based 1T Pixel Sensor
N Rao, VK Mishra - IEEE Sensors Journal, 2023 - ieeexplore.ieee.org
In this article, we investigate a novel intended source one transistor pixel sensor (IS 1T
PIXEL SENSOR) at 22-nm gate technology. The proposed pixel sensor is demonstrated with …
PIXEL SENSOR) at 22-nm gate technology. The proposed pixel sensor is demonstrated with …
Investigation of junction capacitance in Zener tunnelling tunnel diode partially depleted silicon on insulator
Junction capacitance variation in Zener Tunnelling Tunnel Diode Partially Depleted Silicon
On Insulator (ZT-TDPDSOI), due to the geometry effects of source and drain are discussed in …
On Insulator (ZT-TDPDSOI), due to the geometry effects of source and drain are discussed in …
Reduction of Subthreshold Swing in Zener Tunnelling-Tunnel Diode Partially Depleted Silicon On Insulator
S Baby, A Pradeep - 2022 International Conference on …, 2022 - ieeexplore.ieee.org
This work reports subthreshold swing reduction in Zener tunneling-tunnel diode partialy
depleted silicon on insulator (ZT-TD-PDSOI). A highly efficient metal oxide semiconductor …
depleted silicon on insulator (ZT-TD-PDSOI). A highly efficient metal oxide semiconductor …
Analysis of Si₃N₄ based n-FDSOI and p-FDSOI MOSFETS for CMOS Application
In this paper, analysis of a Si 3 N 4 based n-and p-FDSOI MOSFET is presented. The
structures of the devices are very similar to the conventional FDSOI MOSFET. Because of …
structures of the devices are very similar to the conventional FDSOI MOSFET. Because of …
[PDF][PDF] Analytical modeling of junction capacitance using Trapezoidal Approximation for source and drain Engineered Partially depleted Silicon on Insulator.
S Baby, A Pradeep, US Shikha - 2022 - scholar.archive.org
Junction capacitance variation in Source-Drain Engineered Partially Depleted Silicon On
Insulator (SDE-PDSOI), due to the geometry effects of source and drain are discussed in this …
Insulator (SDE-PDSOI), due to the geometry effects of source and drain are discussed in this …
[PDF][PDF] Comparative Analysis of the Drain Current in a 7nm and 14nm Fully Depleted Silicon-On-Insulator (SOI) MOSFET
This research investigates the influence of temperature on the drain current of a 7nm and
14nm Silicon-on-Insulator (SOI) MOSFET with Silicon (Si) and Gallium Arsenide (GaAs) as …
14nm Silicon-on-Insulator (SOI) MOSFET with Silicon (Si) and Gallium Arsenide (GaAs) as …