The addition of two binary numbers is the fundamental and most often used arithmetic
operation on microprocessors, digital signal processors (DSP), and data-processing …

Addition is a vital arithmetic operation and acts as a building block for synthesizing all other
operations. A high-performance adder is one of the key components in the design of …

A 3-2 counter and a 4-2 compressor are the basic components in the partial product
summation tree of a parallel array multiplier. A new high-speed and low-power design of …

We present new design and analysis techniques for the synthesis of parallel multiplier
circuits that have smaller predicted delay than the best current multipliers. VG Oklobdzija et …

Full adder is one of the fundamental digital block in the many electronic circuits. As the day
by day scaling down the technology (Deep-sub micron level) power consumption becomes …

This paper focuses on fixed-width multipliers with linear compensation function by
investigating in detail the effect of coefficients quantization. New fixed-width multiplier …

Booth encoding is believed to yield faster multiplier designs with higher energy
consumption. 16x16-bit Booth and Non-Booth multipliers are analyzed in energy and delay …

Wallace tree multipliers provide a power-efficient strategy for high speed multiplication. The
use of high speed 7: 3 counters in the Wallace tree reduction can further improve the …

Column compression multipliers are frequently used in high-performance computer systems
due to their short worst case delay. This paper examines the area, delay, and power …

Hierarchy multiplier is attractive because of its ability to carry the multiplication operation
within one clock cycle. The existing hierarchical multipliers occupy more area and also …