Accelerating neural network inference on FPGA-based platforms—A survey
R Wu, X Guo, J Du, J Li - Electronics, 2021 - mdpi.com
The breakthrough of deep learning has started a technological revolution in various areas
such as object identification, image/video recognition and semantic segmentation. Neural …
such as object identification, image/video recognition and semantic segmentation. Neural …
Efficient FPGA and ASIC realizations of a DA-based reconfigurable FIR digital filter
This brief presents efficient distributed arithmetic (DA)-based approaches for high-
throughput reconfigurable implementation of finite-impulse response (FIR) filters whose filter …
throughput reconfigurable implementation of finite-impulse response (FIR) filters whose filter …
Optimization of band-limited DSP-aided 25 and 50 Gb/s PON using 10G-class DML and APD
P Torres-Ferrera, H Wang, V Ferrero… - Journal of Lightwave …, 2020 - opg.optica.org
The increasing demand for network capacity is driving the development of next-generation
high-speed Passive Optical Networks (PON) supporting 25 and 50 Gbps. One solution to …
high-speed Passive Optical Networks (PON) supporting 25 and 50 Gbps. One solution to …
Reconfigurable convolutional kernels for neural networks on FPGAs
Convolutional neural networks (CNNs) gained great success in machine learning
applications and much attention was paid to their acceleration on field programmable gate …
applications and much attention was paid to their acceleration on field programmable gate …
[图书][B] Multiple constant multiplication optimizations for field programmable gate arrays
M Kumm, P Zipf - 2016 - Springer
As silicon technology advances, field programmable gate arrays appear to gain ground
against the traditional ASIC project starts, reaching out to form the mainstream …
against the traditional ASIC project starts, reaching out to form the mainstream …
A natively fixed-point run-time reconfigurable FIR filter design method for FPGA hardware
J Goldsmith, LH Crockett… - IEEE Open Journal of …, 2022 - ieeexplore.ieee.org
We present a natively fixed-point filter design method that targets FPGA-based
Reconfigurable Finite Impulse Response (RFIR) filters for Software Defined Radio …
Reconfigurable Finite Impulse Response (RFIR) filters for Software Defined Radio …
Reconfigurable constant multiplication for FPGAs
This paper introduces a new heuristic to generate pipelined run-time reconfigurable
constant multipliers for field-programmable gate arrays (FPGAs). It produces results close to …
constant multipliers for field-programmable gate arrays (FPGAs). It produces results close to …
Analysis and implementation of high performance reconfigurable finite impulse response filter using distributed arithmetic
The finite impulse response (FIR) digital filters are commonly used in many digital signal
processing systems. For higher order filters the implementation of reconfigurable random …
processing systems. For higher order filters the implementation of reconfigurable random …
Dynamically Configurable FIR Filters Based on Serial MACs and Systolic Arrays
FIR (Finite Impulse Response) filters are widely used in digital communication systems,
digital image processing, and many other fields. A great deal of research has been done on …
digital image processing, and many other fields. A great deal of research has been done on …
DyRecMul: Fast and Low-Cost Approximate Multiplier for FPGAs using Dynamic Reconfiguration
Multipliers are widely-used arithmetic operators in digital signal processing and machine
learning circuits. Due to their relatively high complexity, they can have high latency and be a …
learning circuits. Due to their relatively high complexity, they can have high latency and be a …