A broadband mixed-signal CMOS power amplifier with a hybrid class-G Doherty efficiency enhancement technique
This paper presents a broadband mixed-signal CMOS power amplifier (PA) with a hybrid
Class-G Doherty architecture for PA efficiency enhancement up to the deep power back-off …
Class-G Doherty architecture for PA efficiency enhancement up to the deep power back-off …
A 40% PAE frequency-reconfigurable CMOS power amplifier with tunable gate–drain neutralization for 28-GHz 5G radios
In this paper, a high-efficiency frequency-reconfigurable CMOS power amplifier (PA) design
technique is presented at 24 and 28 GHz using integrated tunable neutralization and …
technique is presented at 24 and 28 GHz using integrated tunable neutralization and …
A 2.4 GHz CMOS class-F power amplifier with reconfigurable load-impedance matching
M Gilasgar, A Barlabé, L Pradell - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
A novel reconfigurable CMOS class-F power amplifier (PA) at 2.4 GHz is proposed in this
paper. It is able to match the output load variations mainly due to the effect of hand and head …
paper. It is able to match the output load variations mainly due to the effect of hand and head …
A quadrature digital power amplifier with hybrid Doherty and impedance boosting for complex domain power back-off efficiency enhancement
A quadrature digital power amplifier (PA) with hybrid Doherty and impedance boosting
(HDIB) technique is presented for deep power back-off (PBO) efficiency enhancement in the …
(HDIB) technique is presented for deep power back-off (PBO) efficiency enhancement in the …
Active inductor-based tunable impedance matching network for RF power amplifier application
A Saberkari, S Ziabakhsh, H Martinez, E Alarcón - Integration, 2016 - Elsevier
This paper presents the use of a new structure of active inductor named cascoded flipped-
active inductor (CASFAI) in a T-type high-pass tunable output matching network of a class-E …
active inductor (CASFAI) in a T-type high-pass tunable output matching network of a class-E …
A 2.4-GHz CMOS power amplifier with an integrated antenna impedance mismatch correction system
To prevent the performance degradation of a power amplifier (PA) from an antenna
impedance mismatch, we propose a fully integrated PA with an automatic antenna-mismatch …
impedance mismatch, we propose a fully integrated PA with an automatic antenna-mismatch …
A 60-GHz power amplifier design using dual-radial symmetric architecture in 90-nm low-power CMOS
JF Yeh, JH Tsai, TW Huang - IEEE transactions on microwave …, 2013 - ieeexplore.ieee.org
An innovative on-chip 3-D power amplifier (PA) architecture for M-way power-combined
CMOS PAs by using the proposed dual-radial symmetric architecture is presented. It …
CMOS PAs by using the proposed dual-radial symmetric architecture is presented. It …
A cascode feedback bias technique for linear CMOS power amplifiers in a multistage cascode topology
A novel feedback bias technique for a multistage cascode topology is developed to improve
the linearity and reliability of power amplifiers (PAs). Due to the large parasitic capacitance …
the linearity and reliability of power amplifiers (PAs). Due to the large parasitic capacitance …
A CMOS antiphase power amplifier with an MGTR technique for mobile applications
In this paper, a CMOS antiphase power amplifier (PA) is presented with a multigate
transistor (MGTR) technique that improves its linearity. The drive stage of the PA is biased in …
transistor (MGTR) technique that improves its linearity. The drive stage of the PA is biased in …
A compact broadband mixed-signal power amplifier in bulk CMOS with hybrid class-G and dynamic load trajectory manipulation
This paper presents a mixed-signal power amplifier (PA) with real-time hybrid Class-G and
dynamic load trajectory manipulation (DLTM) operation that achieves PA efficiency …
dynamic load trajectory manipulation (DLTM) operation that achieves PA efficiency …