Thickness dependence of the resistivity of platinum-group metal thin films

S Dutta, K Sankaran, K Moors, G Pourtois… - Journal of Applied …, 2017 - pubs.aip.org
We report on the thin film resistivity of several platinum-group metals (Ru, Pd, Ir, and Pt).
Platinum-group thin films show comparable or lower resistivities than Cu for film thicknesses …

Mini-review: Modeling and performance analysis of nanocarbon interconnects

WS Zhao, K Fu, DW Wang, M Li, G Wang, WY Yin - Applied Sciences, 2019 - mdpi.com
As the interconnect delay exceeds the gate delay, the integrated circuit (IC) technology has
evolved from a transistor-centric era to an interconnect-centric era. Conventional metallic …

Analysis of Cu-graphene interconnects

ZH Cheng, WS Zhao, DW Wang, J Wang, L Dong… - IEEE …, 2018 - ieeexplore.ieee.org
Due to its ultrathin feature, graphene has been recently proposed as diffusion barrier layer
for Cu wires. This paper is geared toward developing an equivalent single-conductor (ESC) …

Control of Cu morphology on TaN barrier and combined Ru-TaN barrier/liner substrates for nanoscale interconnects from atomistic kinetic Monte Carlo simulations

S Aldana, CL Nies, M Nolan - arXiv preprint arXiv:2410.06133, 2024 - arxiv.org
The miniaturization of electronic devices brings severe challenges in the deposition of metal
interconnects in back end of line processing due to a continually decreasing volume …

Crosstalk reduction in copper on‐chip interconnects with graphene barrier for ternary logic applications

DM Badugu - International Journal of Circuit Theory and …, 2020 - Wiley Online Library
This paper presents the investigations of crosstalk effects in ternary logic‐based coupled
interconnects. The crosstalk analysis is investigated for coupled copper interconnects and …

[HTML][HTML] The role of Ru passivation and doping on the barrier and seed layer properties of Ru-modified TaN for copper interconnects

S Kondati Natarajan, CL Nies, M Nolan - The Journal of chemical …, 2020 - pubs.aip.org
Size reduction of the barrier and liner stack for copper interconnects is a major bottleneck in
further down-scaling of transistor devices. The role of the barrier is to prevent diffusion of Cu …

Near-field radiated from carbon nanotube and graphene-based nanointerconnects

AG D'Aloia, WS Zhao, G Wang… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
The electromagnetic field radiated by Cu-graphene interconnects is predicted in the
frequency domain using the equivalent single conductor formulation, and it is compared with …

Optimization of Physical Failure Analysis Process to Minimize Transistors Degradation from Electron Beam for Advance Technology Nodes

CE Chow, WM Goh, D Zhu, TP Chua… - … Symposium on the …, 2023 - ieeexplore.ieee.org
In this paper, authors investigated the effects of SEM Vacc during Physical Failure Analysis
on transistor's electrical parameters, specifically I-off, I-sat and Vt. It was verified that 2kV …

Leveraging design diversity to counteract process variation: theory, method, and FPGAtoolchain to increase yield and resiliencein‐situ

AA Alzahrani, RF DeMara - IET Computers & Digital …, 2019 - Wiley Online Library
With continued scaling of integrated circuits into deep nanoscale fabrication technologies,
the aggravated effects of reliability degradation and variability in process parameters can …

Design closure

PJ Osler, JM Cohn, D Chinnery - Electronic Design Automation for …, 2017 - taylorfrancis.com
Design Closure Page 1 295 CONTENTS 13.1 Introduction 296 13.1.1 Evolution of the Design
Closure Flow 296 13.1.1.1 ASIC Design Flow 297 13.1.1.2 Evolution of Design Constraints …