In situ radiation hardness study of amorphous Zn–in–Sn–O thin-film transistors with structural plasticity and defect tolerance

D Ho, S Choi, H Kang, B Park, MN Le… - … Applied Materials & …, 2023 - ACS Publications
Solution-processed metal-oxide thin-film transistors (TFTs) with different metal compositions
are investigated for ex situ and in situ radiation hardness experiments against ionizing …

Designs of two quadruple-node-upset self-recoverable latches for highly robust computing in harsh radiation environments

A Yan, Z Li, J Cui, Z Huang, T Ni… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
This article proposes two quadruple node upset (QNU) recoverable latches, namely QNU-
recoverable and high-impedance-state (HIS)-insensitive latch (QRHIL) and QRHIL-LC (low …

Nonvolatile latch designs with node-upset tolerance and recovery using magnetic tunnel junctions and CMOS

A Yan, L Wang, J Cui, Z Huang, T Ni… - … Transactions on Very …, 2023 - ieeexplore.ieee.org
As semiconductor technologies scale down, radiative-particle-induced soft errors and static
power consumption are becoming major concerns for digital circuits. Magnetic-tunnel …

RETRACTED: Effects of tensile overload on fatigue crack growth in AM60 magnesium alloys

SA Hashemi, K Farhangdoost, W Ma, DG Moghadam… - 2022 - Elsevier
After a thorough investigation, the Editor in Chief has concluded that this article must be
retracted due to serious errors, such as including 24 inappropriate references, a duplication …

A highly robust and low-power real-time double node upset self-healing latch for radiation-prone applications

S Kumar, A Mukherjee - … on Very Large Scale Integration (VLSI …, 2021 - ieeexplore.ieee.org
This work presents a single event double node upset (SEDNU) self-healing (DNUSH) latch
to meet the high-robustness requirement of the applications used in a harsh radiation …

Low-overhead triple-node-upset-tolerant latch design in 28-nm CMOS

X Chen, Y Bai, J Cao, L Wang, X Zhou… - … Transactions on Very …, 2023 - ieeexplore.ieee.org
As the feature size of the nanoscale CMOS keeps scaling down, the charge sharing effect is
becoming more and more prominent, and the occurrence possibility of the triple-node upset …

[HTML][HTML] Investigations on effect of arrangement of fins on melting performance of vertical PCM enclosure (3D simulation using FVM methods)

S Liu, H Bai, Q Xu, P Jiang, A Mohamed - Alexandria Engineering …, 2022 - Elsevier
Present investigation, effect of different forms of rectangular fins on melting performance of a
vertical enclosure filled by with phase change material (PCM) was examined. Three …

Nature‐inspired virtual machine placement mechanisms: A systematic review

Y Kong, Y He, K Abnoosian - Concurrency and Computation …, 2022 - Wiley Online Library
Cloud data centers do not completely use their resources, resulting in resource
underutilization. Cloud computing companies primarily leverage virtualization technologies …

A triple-node upset self-healing latch for high speed and robust operation in radiation-prone harsh-environment

S Kumar, A Mukherjee - Microelectronics Reliability, 2022 - Elsevier
With continuous advancement in technology, latches have become highly susceptible to
radiation induced soft-errors such as multi-node-upsets (MNU). To effectively resilient the …

Highly reliable quadruple-node upset-tolerant D-latch

S Hatefinasab, A Ohata, A Salinas, E Castillo… - IEEE …, 2022 - ieeexplore.ieee.org
As CMOS technology scaling pushes towards the reduction of the length of transistors,
electronic circuits face numerous reliability issues, and in particular nodes of D-latches at …