N Beringuier-Boher, K Gomina, D Hely… - 2014 17th Euromicro …, 2014 - ieeexplore.ieee.org
Supply voltage glitches are a well-known fault injection method used to attack electronic circuits. The aim of this paper is to identify the specific threats of mixed signal systems and to …
A Askeland, S Nikova, V Nikov - IACR Transactions on Cryptographic …, 2024 - tches.iacr.org
Over the last decades, fault injection attacks have been demonstrated to be an effective method for breaking the security of electronic devices. Some types of fault injection attacks …
RT de Souza, SD Zorzo… - 2015 IEEE Frontiers in …, 2015 - ieeexplore.ieee.org
Scrum framework disseminates principles that guarantee a dynamic and adaptable Software development process. Supporting the software engineering teaching using agile …
BP Das, H Onodera - IEEE Transactions on Very Large Scale …, 2014 - ieeexplore.ieee.org
In this paper, a metastability immune warning flip-flop (FF) is proposed, which consists of an edge detector, a warning window generator, and a warning detector along with a traditional …
NF Galathy, B Yuce, P Schaumont - Fundamentals of IP and SoC Security …, 2017 - Springer
Fault injection is a powerful hacking tool, affecting all forms of cryptography. In this chapter, we describe common fault injection mechanisms, and common fault analysis techniques …
Y Shionoiri - US Patent 8,994,430, 2015 - Google Patents
To reduce power consumption of a circuit (TEDC) which detects timing errors in a main flip- flop by determining whether or not output data signals of the main flip-flop and a shadow flip …
HH Huang, H Cheng, C Chu… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
Timing resilient designs can remove variation margins by adding error detecting logic (EDL) that detects timing errors when execution completes within a resiliency window. Speeding …
Every day, we rely on hundreds of electronic systems embedded in the cars we drive, the appliances in our homes, and important infrastructure that supports our communities. End …
Timing resilient designs can remove variation margins by adding error detecting logic (EDL) that detects timing errors when execution completes within a resiliency window. Speeding …