A physics-based 3-D potential and threshold voltage model for undoped triple-gate FinFET with interface trapped charges
A threshold voltage model based on the solution of the three-dimensional (3-D) Poisson's
equation for an undoped triple-gate (TG) fin-shaped field-effect transistor (FinFET) with …
equation for an undoped triple-gate (TG) fin-shaped field-effect transistor (FinFET) with …
Analytical model of hot carrier degradation in uniaxial strained triple-gate FinFET for circuit simulation
The triple-gate (TG) SOI FinFET has well suppressed short-channel effects compared to
planar MOSFET due to increased gate voltage controllability. However, the hot carrier …
planar MOSFET due to increased gate voltage controllability. However, the hot carrier …
Evaluation of mirror full adder circuit reliability performance due to negative bias temperature instability (NBTI) effects based on different defect mechanisms
IB Shaari, MF Zainudin, MSA Saini, H Hussin… - AIP Conference …, 2017 - pubs.aip.org
Negative bias temperature instability (NBTI) is an aging effect that can cause the threshold
voltage to be shifted hence reduce the drain current. This will subsequently leads to main …
voltage to be shifted hence reduce the drain current. This will subsequently leads to main …
Hot Carrier Reliability in 45 nm Strained Si/relaxed Si1−xGex CMOS Based SRAM Cell
Hot Carrier Injection is one of the serious reliability issues of the NMOS transistors in the
nanoscale regime. The effect of channel strain on hot carrier reliability of 45 nm strained …
nanoscale regime. The effect of channel strain on hot carrier reliability of 45 nm strained …
Negative bias temperature instability benefits on power reduction techniques
KS Sreekala, S Krishnakumar - 2018 International Conference …, 2018 - ieeexplore.ieee.org
This article stabilizes the significant link between static power and reliability. More
particularly, shows the general leakage reduction techniques provide a valid solution to …
particularly, shows the general leakage reduction techniques provide a valid solution to …
Analytical modeling of random discrete traps induced threshold voltage fluctuations in double-gate MOSFET with HfO2/SiO2 gate dielectric stack
An analytical model of threshold voltage fluctuations due to random discrete traps at Si/SiO 2
interface and in gate oxide regions for undoped double-gate (DG) MOSFET with high-k/SiO …
interface and in gate oxide regions for undoped double-gate (DG) MOSFET with high-k/SiO …
Reliability analysis of a Delay-Locked Loop under HCI and BTI Degradation
T Dhar, SS Sapatnekar - 2019 IEEE International Reliability …, 2019 - ieeexplore.ieee.org
This paper studies the impact of hot carrier injection and bias temperature instability on a
mixed-signal delay locked loop, at the block and system levels. Aging affects delays on the …
mixed-signal delay locked loop, at the block and system levels. Aging affects delays on the …
[PDF][PDF] NBTI effects on circuit reliability performance of 4-bit Johnson counter based on different simulation configuration
Negative-bias temperature instability (NBTI) has become a serious circuit reliability concern
as technology nodes decrease to nanometer scales. This paper presents comprehensive …
as technology nodes decrease to nanometer scales. This paper presents comprehensive …
Impact of NBTI induced variations on FinFET based Vernier delay line time to digital converter
The Negative Bias Temperature Instability (NBTI) is one of the serious reliability issues of the
p-type MOS based transistors. The downscaling of gate oxide thickness to reestablish the …
p-type MOS based transistors. The downscaling of gate oxide thickness to reestablish the …