Nanosheet field effect transistors-A next generation device to keep Moore's law alive: An intensive study

J Ajayan, D Nirmal, S Tayal, S Bhattacharya… - Microelectronics …, 2021 - Elsevier
Incessant downscaling of feature size of multi-gate devices such as FinFETs and gate-all-
around (GAA) nanowire (NW)-FETs leads to unadorned effects like short channel effects …

A critical review on performance, reliability, and fabrication challenges in nanosheet FET for future analog/digital IC applications

S Valasa, S Tayal, LR Thoutam, J Ajayan… - Micro and …, 2022 - Elsevier
This article critically reviews the fabrication challenges, emerging materials (wafer, high-k
oxide, gate metal, channel materials), dimensional influences, thermal effects, growth …

p-Type trigate junctionless nanosheet MOSFET: analog/RF, linearity, and circuit analysis

BS Vakkalakula, N Vadthiya - … Journal of Solid State Science and …, 2021 - iopscience.iop.org
Abstract Silicon (Si) nanosheet (NS) metal-oxide semiconductor field effect transistors
(MOSFETs) are realized as an outstanding structure to obtain better area scaling and power …

Computational perspective on recent advances in quantum electronics: from electron quantum optics to nanoelectronic devices and systems

J Weinbub, R Kosik - Journal of Physics: Condensed Matter, 2022 - iopscience.iop.org
Quantum electronics has significantly evolved over the last decades. Where initially the clear
focus was on light–matter interactions, nowadays approaches based on the electron's wave …

Investigation of thermal stress effects on subthreshold conduction in nanoscale p-FinFET from Multiphysics perspective

H Duan, E Li, Q Huang, D Li, Z Chu, J Wang… - Journal of Applied …, 2024 - pubs.aip.org
The rising temperature due to a self-heating or thermal environment not only degrades the
subthreshold performance but also intensifies thermal stress, posing a severe challenge to …

[PDF][PDF] Deep Insight into Channel Engineering of Sub-3 nm-Node P-Type Nanosheet Transistors with a Quantum Transport Model.

A Khaliq, S Zhang, JZ Huang, K Kang… - Progress In …, 2022 - jpier.org
Based on a self-consistent Schrödinger-Poisson solver and top-of-the-barrier model, a
quantum transport simulator of p-type gate-all-around nanosheet FET is developed. The …

A hybrid streamline upwind finite volume-finite element method for semiconductor continuity equations

DW Wang, WS Zhao, ZM Zhang, Q Liu… - … on Electron Devices, 2021 - ieeexplore.ieee.org
This article presents the construction and analysis of a hybrid numerical method for the
discretization of the convection-dominated nonlinear carrier transport process in …

Benchmarking and optimization of circular double gate transistor (CDGT) for sub 10 nm nodes

K Sagar, S Maheshwaram - Silicon, 2023 - Springer
Abstract Circular Double Gate Transistors (CDGTs) are one of the alternative promising
devices to overcome short-channel effects (SCEs) with improved electrostatic control by two …

Rigorous modeling and investigation of low-field hole mobility in silicon and germanium gate-all-around nanosheet transistors

S Zhang, H Xie, JZ Huang, W Chen… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
The low-field hole mobility in p-type inversion-mode silicon (Si) and germanium (Ge)
nanosheet (NS) transistors is rigorously calculated by a physics-based theoretical model …

Finite Element Approach Based Numerical Framework for Device Simulator

DW Wang, Q Zhang, H Wan… - IEEE Transactions on …, 2025 - ieeexplore.ieee.org
In this work, a finite element method (FEM)-based numerical framework is proposed to
effectively calculate the drift-diffusion equations and compiled into a parallel computing …