The high access latency of DRAM continues to be a performance challenge for
contemporary microprocessor systems. Prefetching is a well-established technique to …

Superscalar out-of-order cores deliver high performance at the cost of increased complexity
and power budget. In-order cores, in contrast, are less complex and have a smaller power …

Flexible instruction scheduling is essential for performance in out-of-order processors. This
is typically achieved by using CAM-based Instruction Queues (IQs) that provide complete …

Wearable computing systems have spurred many opportunities to continuously monitor
human bodies with sensors worn on or implanted in the body. These emerging platforms …

The single-thread performance of a processor improves the capability of the entire system by
reducing the critical path latency of programs. Typically, conventional superscalar …

The performance gap between in-order (InO) and out-of-order (OoO) cores comes from the
ability to dynamically create highly optimized instruction issue schedules. In this work, we …

Single-thread performance and throughput often pose different design constraints and
require compromises. Mainstream CPUs today incorporate a non-trivial number of cores …

Out-of-order superscalar processors are currently the only architecture that speeds up
irregular programs, but they suffer from poor power efficiency. To tackle this issue, we …

Out-of-order cores provide high performance at the cost of energy efficiency. Dynamic
scheduling is one of the major contributors to this: generating highly optimized issue …

Simultaneous multithreading (SMT) out-of-order cores waste a significant portion of
structural out-of-order core resources on instructions that do not need them. These …