This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR)
analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure …

A successive approximation analog-to-digital converter (ADC) is presented operating at
ultralow supply voltages. The circuit is realized in a 0.18-μm standard CMOS technology …

Charge redistribution based successive approximation (SA) analog-to-digital converter
(ADC) has the advantage of power efficiency. Split capacitor digital-to-analog converter …

We present in this paper an overview of circuit techniques dedicated to design reliable low-
voltage (1-V and below) analog functions in deep submicron standard CMOS processes …

Three different CMOS dynamic comparator topologies for pipeline A/D converters, resistive
divider, differential pair, and charge distribution comparators, are analyzed. The topologies …

For four decades the evolution of integrated circuits has followed Moore's law, according to
which the number of transistors per square millimeter of silicon doubles every 18 months. At …

A low-power 14-b 100-MS/s analog-to-digital converter (ADC) is described. The prototype
ADC achieves low-power consumption and small die area by sharing an opamp between …

A 0.6-V 2-2 cascaded audio delta-sigma ADC is described. It uses a resistor-based
sampling technique which achieves high linearity and low-voltage operation without …

Power and area saving concepts such as operational amplifier (opamp) bias current reuse
and capacitive level shifting are used to lower the analog power of a 10-bit pipelined analog …

A 1-V, 8-bit pipelined ADC is realized using multi-phase switched-opamp (SO) technique. A
novel loading-free architecture is proposed to reduce the capacitive loading and to improve …