This work revisits the design of crossbar and high-radix interconnects in light of advances in
circuit and layout techniques that improve crossbar scalability, obviating the need for deep …

In this paper, we explore the challenges in scaling on-chip networks towards kilo-core
processors. Current low-radix topologies optimize for fast local communication, but do not …

Mapping application task graphs on intellectual property (IP) cores into network-on-chip
(NoC) is a non-deterministic polynomial-time hard problem. The evolution of network …

Networks on chip (NoC) emerged as a promising alternative to bus-based interconnect
networks to handle the increasing communication requirements of the large systems on …

Due to the advancement of transistor technology, a single chip processor can now have
hundreds of cores. Network-on-Chip (NoC) has been the superior interconnect fabric for …

NoC architectures are considered the next generation of communication infrastructure for
future systems-on-chip. Selection of the network architecture and mapping of IP nodes onto …

Application mapping of disseminated intellectual property into Network on Chip (NoC) is a
well-defined NP-Hard problem. Improvement of network performance in NoC is purely …

Mobile agents are no longer a theoretical issue since different architectures for their
realization have been proposed. With the increasing market of electronic commerce it …

Systems On-Chip designs have evolved over time from fairly simple unicore single memory
designs to complex homogeneous/heterogeneous multicore SoC architectures consisting of …

Abstract Network on Chip (NoC) is a discipline research path that primarily addresses the
global communication in System on Chip (SoC). It is inspired and uses the same routing and …