In a method of generating variation-aware library data for statistical static timing analysis
(SSTA), a “synthetic” Gaussian variable can be used to represent all instances of one or …

This paper proposes a novel fast and unified mixed-signal design methodology by
incorporating manufacturing process variation awareness in power, performance, and …

A framework is proposed to perform timing analysis of state-of-art microprocessors
considering the impact of process-voltage-temperature (PVT) variations and the aging effect …

In order to achieve ultra-low power (ULP), ICs are being designed for V DD≤ 0.5 V. At these
low voltages, random dopant fluctuations (RDFs) result in a stochastic component of logic …

(57) ABSTRACT A method is described for simulating the f-sigma timing path delay of an
integrated circuit design when local transistor variations determine the stochastic delay. This …

In nanoscale digital CMOS IC design, the large technology parameter variations have
boosted the interest in statistical performance analysis. As the huge execution time of SPICE …

This paper proposes a methodology for standard cell characterization which contains three
models: an input capacitance model, a sensitivity model for variational resistive-capacitive …

For CMOS feature size of 65 nm and below, local (or intra-die or within-die) variations in
transistor Vt contribute stochastic variation in logic delay that is a large percentage of the …

Multivariate adaptive regression splines (MARSP) is a nonparametric regression method. It
is an adaptive procedure which does not have any predetermined regression model. With …

Process variations are of great concern in modern technologies. Early prediction of their
effects on the circuit performance and parametric yield is extremely useful. In today's …