A novel explicit-pulsed dual-edge triggered sense-amplifier flip-flop (DET-SAFF) for low-
power and high-performance applications is presented in this paper. By incorporating the …

Latches and flip-flops play important roles in the building of digital CMOS circuits. In the
paper, a new low-power positive level-sensitive latch and a simple and innovative dynamic …

New complex and Low Power systems are being implemented using advanced Electronic
Design Automation (EDA) tools. Low power designs are not only used in small size …

Double-edge triggered flip-flops offer a solution to clock power reduction by lowering the
clock frequency and maintaining the same data rate. A compact 9-transistor double-edge …

Clocked flip flops are used to memory in synchronous or clocked series networks, adjusting
the individual clock signal status. Therefore, at these times of clock signal transfer, the state …

A low power high speed 32 Bit ROM circuit implemented on 0.18 µm CMOS process has
been presented in this paper. The circuit is build using a parallel ROM core structure and …

At-speed testing is essential for VLSI ICs implemented in nanometer technologies, operating
at high clock speeds. Traditional scan based methodologies can be used for at-speed …

Flip-flops are critical timing elements in digital circuits which have a large impact on circuit
speed and power consumption. The performance of the Flip-Flop is an important element to …

Power consumption is a major problem of system performance and it is listed as one of the
top three challenges in International Technology for Semiconductor. In practice, a large …

In the research of low power and low voltage in networks, the use and implementation of
dual edge triggered flip flop has gained more attention at the gate level design. The main …