Simulation study of multi-source hetero-junction tfet-based capacitor less 1t dram for low power applications

S Chander, SK Sinha, R Chaudhary - Materials Science and Engineering: B, 2024 - Elsevier
A capacitorless one-transistor dynamic random access memory (1T DRAM) based on multi-
source hetero-junction tunnel field-effect transistor (TFET) is presented in this work. The …

1T-DRAM with shell-doped architecture

MHR Ansari, N Navlakha, JT Lin… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
This paper reports on the usefulness of shell-doped (SD) junctionless (JL) transistor
architecture for operation as capacitorless dynamic random-access memory (1T-DRAM). SD …

Dopingless 1T DRAM: Proposal, design, and analysis

A James, S Saurabh - IEEE Access, 2019 - ieeexplore.ieee.org
In this paper, we have proposed a dopingless 1T DRAM (DL-DRAM) that utilizes the charge
plasma concept. The proposed device employs a misaligned double-gate architecture to …

Design and analysis of dopingless 1T DRAM using work function engineered tunnel field effect transistors

AV Arun, PS Sreelekshmi, J Jacob - Microelectronics Journal, 2022 - Elsevier
In this paper, a dopingless DRAM based on work function engineered Tunnel field effect
transistor is proposed. Gate metal workfunction engineering is done to enhance ON/OFF …

Ferroelectric dual material gate all around TFET architecture for enhanced electrical performance

V Mishra, YK Verma, PK Verma… - 2018 15th IEEE India …, 2018 - ieeexplore.ieee.org
This work examines the device behavior of ferroelectric dual material gate all around tunnel
field effect transistor (FE-DMGAA-TFET). The ferroelectric material manifests the negative …

Two dimensional analytical model for a negative capacitance double gate tunnel field effect transistor with ferroelectric gate dielectric

H Xu - Journal of Semiconductors, 2018 - iopscience.iop.org
Analytical models are presented for a negative capacitance double-gate tunnel field-effect
transistor (NC DG TFET) with a ferroelectric gate dielectric in this paper. The model …

Enhancing multi-functionality of reconfigurable transistors by implementing high retention capacitorless dynamic memory

YV Bhuvaneshwari, A Kranti - Semiconductor Science and …, 2021 - iopscience.iop.org
A key indicator of multi-functional attributes of a transistor is technological competiveness vis-
à-vis existing architectures. Apart from the well-known logic circuit implementation through …

A physics based model for negative capacitance TFET considering variation in ferroelectric parameters

S Chaudhary, B Dewan, D Singh… - Engineering Research …, 2024 - iopscience.iop.org
Here, an explicit analytical model of electrical properties like channel potential, electric field,
drain current, and threshold voltage for a negative capacitance DGTFET structure is …

Improving Retention Time of 1T DRAM using Electrostatic Barrier: Proposal and Analysis

S Singh, E Tiwari, A Gupta… - 2024 37th International …, 2024 - ieeexplore.ieee.org
In this paper, we propose a IT DRAM with an electrostatic barrier to improve the retention
time of the device. The proposed device utilizes a misaligned double-gate to store holes and …

Simulation and Extraction of Dual-Gate TFET With Ferroelectric Material to Preserve Data

A Verma, P Verma… - 2024 Fourth International …, 2024 - ieeexplore.ieee.org
Semiconductor devices are fundamental components of the electronic industry. Due to many
limitations, like sub threshold swing, low switching time, and a low I on/I off ratio, MOSFETs …